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A HW/SW Co-Simulator for System Validation

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Presentation on theme: "A HW/SW Co-Simulator for System Validation"— Presentation transcript:

1 A HW/SW Co-Simulator for System Validation
-- ECE649 Course Project Proposal Weiwen Zhu Dept. ECE McGill University 8/8/2019 A HW/SW Co-Simulator for System Verification

2 A HW/SW Co-Simulator for System Verification
Motivation and Background More functionality in software Low power, high denisity, easy to upgrade HW/SW co-simulator environment Functionality and timing Speed and cost Ptolemy for UCB Hybrid modeling and simulating environment Component based Simulation for Validation 8/8/2019 A HW/SW Co-Simulator for System Verification

3 A HW/SW Co-Simulator for System Verification
Objective Fast simulation of the HW/SW system Apply design pattern for software design Reactive software User interface Communication protocol Hardware resource sharing Multiple processors Buffer 8/8/2019 A HW/SW Co-Simulator for System Verification

4 A HW/SW Co-Simulator for System Verification
Software Structure Implememt as an extension to existing Ptolemy domain Dynamic task tree Parameterize hardware 8/8/2019 A HW/SW Co-Simulator for System Verification

5 A HW/SW Co-Simulator for System Verification
Using OO design pattern Reactor pattern for message dispatch Subscriber pattern Non-blocking buffering pattern 8/8/2019 A HW/SW Co-Simulator for System Verification

6 A HW/SW Co-Simulator for System Verification
Simulation for Testing Simulation for Verification find constrains Simulation for Validation Pass / Fail criteria Simulation for Synthesis Find the best solution under the timing constrains 8/8/2019 A HW/SW Co-Simulator for System Verification


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