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NP Completeness of Discrete Wire Sizing

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Presentation on theme: "NP Completeness of Discrete Wire Sizing"— Presentation transcript:

1 NP Completeness of Discrete Wire Sizing
K. Moiseev, A. Kolodny and S. Wimer Technion, EE Dept. Bar Ilan Univ., School of Engineering December 2010

2 Interconnect Signal Model
driver’s resistance receiver’s load line resistance signal's activity, 0<= AF <=1 line-to-line coupling Using Elmore delay model, simple, inaccurate but with high fidelity December 2010

3 Interconnect Bus Model
σ0 A σi σn-1 σn-2 Wi Si Si+1 Ri Ci L December 2010

4 Discrete Wire Sizing In 22nm everything is discrete: devices, width, spacing Only very few wire sizes are allowed: 3-5 widths and spaces Not all combinations are allowed Optimal power-delay turns from continuous to discrete optimization problem Problem is NP-hard (Moiseev, Kolodny & Wimer, J. Comb. Optim. 2010) Sizing optimization for power-delay is solved by dynamic programming (Moiseev, Kolodny & Wimer IEEE TCAD 2010). December 2010

5 December 2010

6 MIN_DLYPWR Problem December 2010

7 December 2010

8 December 2010

9 December 2010

10 December 2010

11 December 2010

12 MIN_MAX_DLYPWR Problem
December 2010

13 December 2010

14 December 2010

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