1. This course is basically about silicon chip fabrication, the technologies used to manufacture ICs.

2. INTRODUCTION

5. It is not sufficient any longer to think a silicon oxidation simply a
chemical reaction between silicon and oxygen that grows SiO2.
Today we must understand that detailed bonding between silicon
and oxygen atoms and kinetics that drive this reaction on atomic basis.

6. IC Fabrication Technology: Brief History1
IC Fabrication Technology: Brief History
1940s - setting the stage - the initial inventions that made integrated circuits possible.
In 1945, Bell Labs established a group to develop a semiconductor replacement for the vacuum tube. The group led by William Shockley, included, John Bardeen, Walter Brattain and others.
In 1947 Bardeen and Brattain and Shockley succeeded in creating an amplifying circuit utilizing a point-contact "transfer resistance" device that later became known as a transistor.
In 1951 Shockley developed the junction transistor, a more practical form of the transistor.
By 1954 the transistor was an essential component of the telephone system and the transistor first appeared in hearing aids followed by radios.
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Lecture #1
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7. The transistor invented at Bell lab. in 19472
The transistor invented at Bell lab. in 1947
In 1956 the importance of the invention of the transistor by Bardeen, Brattain and Shockley was recognized by the Nobel Prize in physics. 
Lecture #1

8. 1958 - Integrated circuit invented3
Integrated circuit invented
September 12th 1958 Jack Kilby at Texas instrument had built a simple oscillator IC with five integrated components (resistors, capacitors, distributed capacitors and transistors)
In 2000 the importance of the IC was recognized when Kilby shared the Nobel prize in physics with two others. Kilby was sited by the Nobel committee "for his part in the invention of the integrated circuit
a simple oscillator IC
Lecture #1

9. 1959 - Planar technology invented4
Planar technology invented
Kilby's invention had a serious drawback, the individual circuit elements were connected together with gold wires making the circuit difficult to scale up to any complexity.
By late 1958 Jean Hoerni at Fairchild had developed a structure with N and P junctions formed in silicon. Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions.
In 1959, Robert Noyce also of Fairchild had the idea to evaporate a thin metal layer over the circuits created by Hoerni's process.
The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Planar technology set the stage for complex integrated circuits and is the process used today. 
Planar technology
Lecture #1

10. IC Fabrication Technology: History (cont.)5
IC Fabrication Technology: History (cont.)
Epitaxial deposition developed
Bell Labs developed the technique of Epitaxial Deposition whereby a single crystal layer of material is deposited on a crystalline substrate. Epitaxial deposition is widely used in bipolar and sub-micron CMOS fabrication.  
First MOSFET fabricated
Kahng at Bell Labs fabricates the first MOSFET.
First commercial ICs
Fairchild and Texas Instruments both introduce commercial ICs.
Transistor-Transistor Logic invented
Semiconductor industry surpasses $1-billion in sales
First MOS IC
RCA produces the first PMOS IC.
Lecture #1

11. 6
CMOS invented
Frank Wanlass at Fairchild Semiconductor originated and published the idea of complementary-MOS (CMOS).
It occurred to Wanlass that a complementary circuit of NMOS and PMOS would draw very little current. Initially Wanlass tried to make a monolithic solution, but eventually he was forced to prove the concept with discrete devices.
Enhancement mode NMOS transistors were not yet available and so Wanlass was used a depletion mode device biased to the off-state.
Amazingly CMOS shrank standby power by six orders of magnitude over equivalent bipolar or PMOS logic gates.
On June 18, 1963 Wanlass applied for a patent. On December 5th 1967 Wanlass was issued U.S. Patent # 3,356,858 for "Low Stand-By Power Complementary Field Effect Circuitry".
CMOS forms the basis of the vast majority of all high density ICs manufactured today.
Lecture #1

12. 7
Moore's law
In 1965 Gordon Moore, director of research and development at Fairchild Semiconductor wrote a paper for Electronics entitled "Cramming more components onto integrated circuits".
In the paper Moore observed that "The complexity for minimum component cost has increased at a rate of roughly a factor of two per year". This observation became known as Moore's law, the number of components per IC double every year.
Moore's law was later amended to, the number of components per IC doubles every 18 months.
Moore's law hold to this day.
Lecture #1

13. 1971 - Microprocessor invented8
Microprocessor invented
The combination of the Busicom (Japanese calculator company) and the Intel came together and by 1971 the 4004 the first 4-bit microprocessor was in production. The 4004 processor required roughly 2,300 transistors to implement, used a silicon gate PMOS process with 10µm linewidths, had a 108KHz clock speed. In 1974 Intel introduced the 8080, the first commercially successful microprocessor.
Intel 8008
The 8008 was the 8 bit successor to the 4004 and was used in the Mark-8 computer, one of the first home computers.
The 8008 had 3,500 transistors, a 200kHz clock speed and a 15.2mm2 die size.
Lecture #1

14. 1993-first Pentium processor invented
Intel Pentium I
The Pentium is the first processor from Intel capable of executing more than 1 instruction per clock cycle. The Pentium was manufactured in a silicon gate BiCMOS process with 0.8µm linewidths, required 18 mask layers and had 1 polysilicon layer and 3 metal layers, the Pentium had 3.1 million transistors, a 60 to 66MHz clock speed and a 264mm2 die size.
Semiconductor Industry passes $100-billion.
Mbit DRAM
The 64Mbit DRAM was produced on a CMOS process with 3 to 5 polysilicon layers, 2 to 3 metal layers and 0.35µm minimum features. The resulting product had a 1.5µm2 memory cell size.
Intel Pentium II
The Pentium II was manufactured in a silicon gate CMOS process with 0.35µm linewidths, required 16 mask layers and had 1 polysilicon layer and 4 metal layers, the Pentium II had 7.5 million transistors, a 233 to 300MHz clock speed and a 209mm2 die size.
Mbit DRAM
The 256Mbit DRAM was produced on a CMOS process with 4 to 5 polysilicon layers, 2 to 3 metal layers and 0.25µm minimum features.The product had a die size of approximately 204mm2.
Intel Pentium III
The Pentium III returned to a more standard PGA package and integrated the cache on chip. The Pentium III was manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium III had 28 million transistors, a 500 to 900MHz clock speed and a 140mm2 die size.
Lecture #1

15. 10
Intel Pentium 4
The Pentium 4 introduced an integer unit running at twice the processor speed. The Pentium 4 was manufactured in a silicon gate CMOS process with 0.18µm linewidths, required 21 mask layers and had 1 polysilicon layer and 6 metal layers, the Pentium 4 had 42 million transistors, a 1,400 to 2,500MHz clock speed and a 224mm2 die size
Lecture #1

16. 11
Lecture #1

17. 12
Die size trends
Lecture #1

18. Microprocessor trends 13
year
Lecture #1

19. 14
DRAM trends
Lecture #1

20. The process flow for semiconductor manufacturing is best considered in two sections, the "front-end" and the "back-end"
The "front-end" is wafer processing which is performed in a Wafer Fab area. The process of wafer fabrication is a series of loops, each putting down a layer on the device. Each loop comprises some or all of the major steps of photolithography, etch, strip, diffusion, ion implantation, deposition, and chemical mechanical planarization. At each stage, there are various inspections and measurements performed to monitor the process and equipment. Supporting the entire process is a complex infrastructure of materials supply, waste treatment, support, logistics,and automation. It has the cleanest environment in the world - many times cleaner than the best hospital operating theater. A Fab is one of the most complex industrial facilities to be found anywhere. A state-of-the-art Fab, costing over $1 billion, has a denser capital per square foot than any industry.
The "back-end" is Test, Assembly and Packaging, where the finished wafer is split up into individual die (chips) which are then assembled into packages which can be handled in the final applications. Full functional electrical test is performed at both wafer and package level to ensure outgoing quality.
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21. The wafer growing process is similar to crystal growing experiments that most of us did at school. A seed crystal of silicon is immersed in a bath of molten silicon. It is slowly pulled out, and because crystal growth occurs uniformly in all directions, the cross section is circular and, as it is pulled, it forms a cylindrical ingot of pure silicon. The ingot pulling process lasts for almost 24 hours and produces a cylinder of diameter larger than is desired. The ingot is ground down to the required diameter, and then is sliced into individual wafers.
At this stage, the wafers have a rough texture and need to be finely polished to meet the surface flatness and thickness specifications. To give you an idea of how critical the flatness specification is, consider the following analogy. If an airplane were to fly across the Pacific Ocean and hold its altitude to within 30 feet of the ocean surface, then this would be equivalent to the flatness specification of a wafer.
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22. The whole semiconductor manufacturing process hinges on the use of a photographic process to create the fine featured patterns of the integrated circuit. Each layer of the chip is defined by a specific mask, and there are 16 to 24 mask layers in each IC.
The mask is somewhat like a photographic negative, which is made by patterning a film of chromium on a pure quartz glass plate. These finished plates are called reticles. Reticles are manufactured by very sophisticated and expensive pattern generation equipment, which is driven from the chip design database. The patterns are formed on the chromium plated quartz plated by removing the chromium with either laser or electron-beam driven tools.
As transistor features are reduced, more components are placed on each chip, requiring larger, more complex patterns to be drawn. This all takes longer to write the masks. Each new design or die shrink requires new mask tooling, so this segment is driven by new product acceleration.
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25. Crystalline or contaminate defects will kill the operation of an IC, so it is imperative that the silicon is ultra-pure. In order to create the best possible quality of silicon, a pure layer of silicon is grown on the raw wafer via an epitaxial growth process. This is known as the epi-layer.
This layer is very thin - approximately 3 percent or less of the wafer thickness. As device complexity grows, the need for epi-wafers increases.

26. Photography is the best analogy to describe the photolithography process. The stepper is like a photographic enlarger where a light source projects an image through a lens system onto photographic paper.
In the semiconductor case, the "light bulb" used to be a mercury arc lamp, but for DUV lithography has been replaced by excimer laser light sources. The image comes from our reticle, and this is then projected through a very complex quartz glass lens system on to the wafer which has been coated (spun-on) with an ultra-thin layer of photoresist material. The reticle image is either printed 1:1 in size or reduced by 4:1 or 10:1, depending on the particular stepper. Clearly, for a 4:1 reduction, the features on the reticle need only be one-fourth of those required on the wafer. The exposure time is dependant on many variable including the sensitivity of the resist, lens aperture, etc.
The machine used to do all of this is called a "stepper" because it literally does one die or a few die at a time, then steps to the next die or set of die until it has exposed the entire wafer.
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27. Basic lithography process flow

28. Now we will start to construct the transistors on the wafer
Now we will start to construct the transistors on the wafer. The first step is to heat the epi-wafer to grow an oxide layer - silicon dioxide. At this point, we go to the lithography process, spin on photoresist, bake it to make it harder, expose the reticle step-by step over the wafer, then develop the resist to create the pattern on the wafer.
The deposition, diffusion or implant processes that follow would actually destroy the photoresist, so the next step is to transfer the pattern from the photoresist to the tougher oxidelayer.....
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29. The wafer with patterned photoresist is then put into an oxide etch process to remove the oxide where there is no pattern. This has the effect of transferring the pattern to the oxide, creating barriers of oxide where we do not want subsequent processes to impact the silicon below. The etch may be either a classic wet chemistry or a "dry" etch which uses gas excited by a radio frequency generator to and excited plasma state.
At this point, the photoresist has served its useful purpose and must be removed. This process is called "strip". The stripping of photoresist must beentirely complete since this is an organic material which, if left on the wafer surface, would cause defects. To do this effectively, chipmakers often use both "wet" and "dry" strippers.
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30. The classic approach to creating pockets of silicon with different electrical properties was to deposit a dopant material, such as Boron, on the surface, then diffuse or drive it into the surface of the silicon by exposing it to controlled periods of high temperature.
As device geometries have become smaller, the side-ways diffusion has become more difficult to deal with, so the industry has converted to the ion implantation process. In implant, the dopant molecules are implanted vertically into the surface of the silicon by a high-energy ion beam. This penetrates the silicon vertically without any appreciable side-ways diffusion.
These regions are now doped with negative ions, creating n-type source and drain regions of the transistor in a p-type silicon base. To complete the n-channel CMOS transistor, we must next create the gate region....
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31. By removing and re-growing the oxide layer, we can then repeat the previous lithography, etch and strip processes with a different mask to create a window opening in the oxide where we want to build the transistor's gate region.
The gate is a conductive layer which is separated from the bulk silicon by a thin gate oxide. A positive electrical charge on the gate will create an opposite negative field in the surface of the silicon. This negative field essentially creates a conductive channel between the source and the drain, letting current flow between them.
The gate oxide needs to be thin since the electrical field must transfer across this insulator. Typically, this is made by depositing silicon nitride film via a Chemical Vapor Deposition process (CVD).
The gate itself is either made of polysilicon or a metal. Polysilicon is deposited by a Physical Vapor Deposition (PVD) process, often known as "sputtering".
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32. We saw how an oxide was used as a masking barrier to create diffused areas in the silicon. Various types of oxides are used for other purposes, usually to electrically isolate electrical paths or transistors from one another. Oxides can be grown by oxidizing silicon, or may be deposited on top of any material.
Deep Field Oxides are grown into the silicon after more lithographic masking to electrically isolate each transistor from its adjacent partners.
Dielectric isolation oxides are deposited in layers to insulate the transistors from the interconnecting layers which will be built above.
Passivation oxides are later deposited on top of completed wafers to protect the surface from damage as they are handled and packaged.
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33. Again using reticles and photolithography, contact areas in the silicon dioxide are unmasked so that they can be etched all the way down to the silicon and polysilicon areas of the transistor's source, drain and gate regions.
These holes, called "vias" are essentially chemically "drilled" holes which expose the contacts to the three-terminals of the transistor.
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34. To connect to the transistor's terminals, aluminum is deposited on the surface and down into the via holes. Another lithographic masking step is performed to mask off the areas where aluminum should remain, then a metal etch is performed to remove the excess aluminum. This leaves the metallization contacting only those regions which are required by design.
Another oxide layer is deposited on top of the aluminum to electrically isolate it from subsequent steps. Note that each time a deposition or etch process step is performed, the surface contours get more developed and are often exaggerated.
These surface contours create obstacles or steps which make it difficult to lay down subsequent metal layers. They also make it difficult to spin on photoresist evenly and control the depth of focus for exposure. For these reasons, it is highly desirable to smooth the surface between process steps....
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35. CMP (Chemical Mechanical Planarization) is an abrasive process used for polishing the surface of the wafer flat. It can be performed on both oxides and metals. It involves the use of chemical slurries and a circular (sanding) action to polish the surface of the wafer smooth.
The smooth surface is necessary to maintain photolithographic depth of focus for subsequent steps and also to ensure that aluminum interconnects are not deformed over contour steps.
A simple analogy here is that of an orbital sander used in woodworking. Imagine such a sander used with a wet chemical paste (slurry).
The smoothed surfaces are now ready to have more process steps, adding more layers....
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36. To add the next layer of interconnect, first it is necessary to mask and etch via holes. Those are then filled with a deposited metal such as tungsten or titanium-tungsten, often known as a "plug", which will provide the electrical connection down between two layers of aluminum.
With the plug in place, the next layer of aluminum can be deposited, masked and etched. This process can be repeated for up to 5 or 6 layers of interconnect for complex logic chips. Memory chips typically only have a couple of metal layers.
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37. Inspection and Measurement is a critical area in semiconductor manufacturing. Chipmaking deals with so many state-of-the-art materials, small features and precision, that the ability to measure and monitor the process is vital.
Measurement is defined as the ability to precisely quantify the physical, dimensional, or electrical properties of materials. There are numerous measurement tools used in the Fab to monitor the quality of the process relative to its designed specifications. Generally, if all materials and processes are within specification, the the chip will operate as designed. Measurement typically applies to such items as wafer flatness, film thickness, electrical properties, critical dimensions (CDs), etc.
Inspection is defined as the ability to observe and quantify defects. These tools include optical instruments and, with shrinking features down at the sub-micron level, scanning electron microscopes (SEM) must be used. As fine geometries get down to below 0.2 micron, the ability to observe these defects becomes more challenging and expensive. Inspection typically applies to such items as reticles (masks), wafers, etc.
As chip densities increase, the volume of inspection and measurement data also increases - hence the need for sophisticated software tools for yield data management and analysis.
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38. Defects kill yield and drive up manufacturing cost, so defect inspection is vital in the Fab.
Defects on the masks or wafers can cause electrical short circuits between aluminum lines that are not supposed to be connected together. They can also cause open circuits or breaks in aluminum traces. Either of these is fatal to the functionality of the chip. With millions of transistors per chip, one can see how defect control is critical. Defects originate either from the atmosphere in the Fab (hence the ultra-clean room requirement), or from the materials used, or from the tools that are used. For a given defect density in a Fab/process, the smaller the die, the larger the population of die per wafer, and the lower the statistical impact of the defects. Also, the smaller the defects are in size, the less is the chance that they will cause fatal problems.
It is not only important to get yields up as high as possible, but it is also important to get them up to their attainable level quickly. Time is money, so a fast ramp-up of yield will get a Fab to profitability sooner.
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39. When the finished wafer comes out of the Fab, it is ready for the Test, Assembly and Packaging processes to finish it into a set of good, usable integrated circuits.
Wafer test is often performed at a location near the Fab, so that yield data can be assessed quickly and fed back to correct and optimize the Fab processes. Assembly, Packaging and Final Test and often performed in a totally different facility - often on a different continent.
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40. Wafer probe or test is the first time that chips are tested to see if they function as they were designed to do.
Wafer probe or test is the first time that chips are tested to see if they function as they were designed to do. There are three basic tools used as a set to perform this operation.
First, the wafer prober is a material handling system that takes wafers from their carriers, loads them to to a flat chuck, aligns and positions them precisely under a set of fine contacts on a probe card. Mostly, this test is performed at room temperature, but the prober is increasingly being required to also heat or cool the wafer during test.
Secondly, each input-output or power pad on the die must be contacted by a fine electrical probe. This is done by a probe card, whose job is to translate the small individual die pad features into connections to the tester.
Thirdly, the functional tester or automatic test equipment (ATE) is capable of functionally exercising all of the chip's designed features under software control. Any failure to meet the published specification is identified by the tester and the device is cataloged as a reject. The tester/probe card combination may be able to contact and test more than one die at a time on the wafer. This parallel test capability enhances productivity at wafer probe.
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41. Redundancy Repair is a process step almost exclusively used for memory chips
Redundancy Repair is a process step almost exclusively used for memory chips. The best way to think of this is via the analogy of the spare wheel in a car. The spare is a redundant fifth wheel carried and used in the event a defect occurs in one of the other four. Similarly, a memory is designed with redundant rows and columns (spares) which can be logically replaced for rows or columns which may contain defective memory cells. The replacement is made by special precision tools which take the wafer probe failure data, locate the failed element, and use a laser beam to perform micro-surgery on links to remove the defective element and connect in a replacement.
Carrying "spares" on a die adds cost overhead, but when one sees that yields can be improved through repair by as much as tens of percent, the overhead cost is well justified.
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42. each pad on the die is connected to a corresponding pin on the package frame via a thin gold or aluminum wire (approx " diameter).
Wafers arriving from Probe either have the reject die marked with ink dots or, the come with a map of the defect locations. The first step in Assembly is to saw between each die in both directions and separate or "dice" out the good die.
Next, the good die are die bonded or attached onto the frame of a package. This attach may be with an epoxy adhesive or with a silicon-metal eutectic bond.
Then, each pad on the die is connected to a corresponding pin on the package frame via a thin gold or aluminum wire (approx " diameter). There are new methods of interconnect evolving, such as flip-chip, but wire bond is still the dominant method and is likely to continue to be for many years.
Finally, the bonded die and frame are sealed - either by a molded plastic compound, or by the attachment of a sealed lid.
Depending on the package type, the pins or leads may have to be trimmed and formed to the desired shape for use in applications.
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43. Package test is the last time that chips are tested to see if they function as they were designed to do before leaving the factory. There are three basic tools used as a set to perform this operation.
First, the handler is a material handling system that takes packaged devices from their carriers, loads them into contacts or sockets and sets the environmental temperature as specified.
Secondly, each pin on the chip's package must be contacted by inserting it into a contactor or socket on a custom designed PC board known by many as a DUT Board or Load Board.
Thirdly, the functional tester or automatic test equipment (ATE) is capable of functionally exercising all of the chip's designed features under software control. Any failure to meet the published specification is identified by the tester and the device is binned as a reject. The tester/handler combination may be able to contact and test more than one part at a time in parallel for increased productivity.
Often, chips are tested at more than one temperature, so each chip may be tested two, three or more times before being shipped.
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44. These few slides have expressed conceptual descriptions of the major process steps involved in semiconductor manufacturing. It is not intended that this is an exhaustive or complete list of the 400-plus steps that are typically used to make semiconductors.
We hope that you have enjoyed this tour through chipmaking with us, and encourage you to visit the rest of our website and subscribe to our publications. On a weekly and monthly basis, we write about different elements of semiconductor manufacturing, the companies and the markets.
In the full seminar presentations, we go into more detail on each process step; describe the challenges and opportunities associated with each step; describe some of the new emerging technologies; discuss the Technology Roadmap critical issues; and identify the companies who participate in each sector.
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