1. Unit-2 CENTRAL PROCESSING UNIT

2. CISC In the 1970’s, memory was expansive and small in size,so people designed computers that would pack as many action as possible in a single instruction this saved memory space,but added complexity. The BCD adder that we made is a CISC since it does both add and correct in one instruction. Microprogrammed control unit Large number of instructions (200-500) Instructions can do more than 1 thing (that is, an instruction could carry out 2 or more actions) Many addressing modes Instructions vary in length and format This was the typical form of architecture until the mid 1980s, RISC has become more popular since then although most architectures remain CISC

3. RISC (reduced instruction set computer) A microprocessor that is designed to perform a smaller number Computer instructions so that it can operate at a higher speed Larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation. John Cocke of IBM Research in Yorktown, New York, originated the RISC concept in 1974. About 20% of the instructions in a computer did 80% of the work. The first computer to benefit from this discovery was IBM's PC/XT in 1980. IBM's RISC System/6000 also made use of the idea. The term itself (RISC) is credited to David Patterson, a teacher at the University of California in Berkeley. The concept was used in Sun Microsystems' SPARC microprocessors and led to the founding of what is now MIPS Technologies, part of Silicon Graphics. The RISC concept has led to a more thoughtful design of the microprocessor. Among design considerations are how well an instruction can be mapped to the clock speed of the microprocessor (ideally, an instruction can be performed in one clock cycle); how "simple" an architecture is required; and how much work can be done by the microchip itself without resorting to software help.

4. Some advantages of RISC are: A new microprocessor can be developed and tested more quickly if one of its aims is to be less complicated. Operating system and application programmers who use the microprocessor's instructions will find it easier to develop code with a smaller instruction set. The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor. Higher-level language compilers produce more efficient code than formerly because they have always tended to use the smaller set of instructions to be found in a RISC computer. After the introduction of RISC, any "full-set" instruction computer was said to use complex instruction set computing (CISC).CISC

5. RISC Hardwired control unit Instruction lengths fixed (usually 32 bits long) Instruction set limited (80-100 instructions) Instructions rely mostly on registers, memory accessed only on loads and stores Few addressing modes Easy to pipeline for great speedup in performance

6. RISC Pure RISC machines have the following features 1. All RISC instructions codes have the same number of bits (Typically 32 bit)  CISC instructions can vary and have no fixed length.  Because RISC have fixed instruction code, this makes it a lot easer to be pipelined, this making it faster 2. The RISC instruction set includes only very simple operations that can ideally be executed in a small number of clock cycles.  These instructions can then be moved through a pipeline quickly and not hold the pipeline up  In the BCD adder we would make add and correction two instructions to make it RISC machine and have it easily pipelined

7. RISC 3. RISC instructions for reading data from memory include only a single operand load instruction and a single operand store instruction.  Because of this RISC machines are referred to as “load and store” machines  Most CISC machines have a single instruction to load the operand from memory and then add operand to a register Note doing two things with a single instruction. Just like in our BCD adder  Two advantages of a simple load and store  machine code only takes a few bits  machine code can be quickly decoded, which makes pipelines easier to design

8. RISC 4. The RISC instruction set is designed so that compilers can efficiently translate high-level language constructer to the instruction codes for the machine, and the result is easily portable from one machine to anther.  Compiler writers took little advantage of powerful CISC instructions because they were very machine specific and then not very portable this ended up having compilers that acted like they were on a RISC machine even though they were in CISC machine because this mad it portable  A problem with pure RISC is that it takes many small instructions to do anything, which uses a lot of memory; this excessive use of memory is cold “code bloat”  Apure RISC machine also requires a greater memory bandwidth because we are constantly microprocessors are between RISC and CISC (a combination of both), in order to reduce code bloating.

9. Difference Between RISC and CISC Architecture The architectural design of the CPU is Reduced instruction set computing (RISC) and Complex instruction set computing (CISC). CISC has the capacity to perform multi-step operations or addressing modes within one instruction set. It is the CPU design where one instruction works several low-level acts. like memory storage, loading from memory, and an arithmetic operation. Reduced instruction set computing is a Central Processing Unit design strategy based on the vision that basic instruction set gives a great performance when combined with a microprocessor architecture which has the capacity to perform the instructions by using some microprocessor cycles per instruction. The hardware part of the Intel is named as Complex Instruction Set Computer (CISC), and Apple hardware is Reduced Instruction Set Computer (RISC).

10. https://www.electronicshub.org/risc-and-cisc- architectures/

11. RISCCISC Reduced Instruction Set Computer.Complex Instruction Set Computer. RISC processors have simple instructions taking about one clock cycle. The average clock cycle per instruction (CPI) is 1.5 CSIC processor has complex instructions that take up multiple clocks for execution. The average clock cycle per instruction (CPI) is in the range of 2 and 15. Focus on softwareFocus on hardware. No memory unit. Uses a separate hardware to implement instructions.. It has a memory unit to implement complex instructions. A hard-wired unit of programming.A microprogramming unit. The instruction set is reduced i.e. it has only a few instructions in the instruction set. Many of these instructions are very primitive. The instruction set has a variety of different instructions that can be used for complex operations. CISC has many different addressing modes and can thus be used to represent higher-level programming language statements more efficiently. Complex addressing modes are synthesized using the software. CISC already supports complex addressing modes

12. RISCCISC Multiple register sets are presentOnly has a single register set Highly pipelinedNormally not pipelined or less pipelined The complexity lies with the compiler that executes the program The complexity lies in the micro program Execution time is very less Execution time is very high Code expansion can be a problemCode expansion is not a problem Decoding of instructions is simple.Decoding of instructions is complex Not require external memory for calculations requires external memory for calculations The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power Architecture, and SPARC. Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family, AMD and Intel x86 CPUs. RISC architecture is used in high-end applications such as video processing, telecommunications and image processing. CISC architecture is used in low-end applications such as security systems, home automation, etc.

13. Pipelining Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing and executing instructions in an orderly process. It is also known as pipeline processing. Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. Pipelining increases the overall instruction throughput. In pipeline system, each segment consists of an input register followed by a combinational circuit. The register is used to hold data and combinational circuit performs operations on it. The output of combinational circuit is applied to the input register of the next segment.

14. Types of Pipeline Arithmetic Pipeline Instruction Pipeline Arithmetic Pipeline Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations, multiplication of fixed point numbers etc. For example: The input to the Floating Point Adder pipeline is: X = A*2^a Y = B*2^b Here A and B are mantissas (significant digit of floating point numbers), while a and b are exponents. The floating point addition and subtraction is done in 4 parts: 1. Compare the exponents. 2. Align the mantissas. 3. Add or subtract mantissas 4. Produce the result. Registers are used for storing the intermediate results between the above operations.

15. Instruction Pipeline In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system. An instruction pipeline reads instruction from the memory while previous instructions are being executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segments of equal duration.

17. Pipeline Conflicts There are some factors that cause the pipeline to deviate its normal performance. Some of these factors are given below 1. Timing Variations: All stages cannot take same amount of time. This problem generally occurs in instruction processing where different instructions have different operand requirements and thus different processing time. 2. Data Hazards: When several instructions are in partial execution, and if they reference same data then the problem arises. We must ensure that next instruction does not attempt to access data before the current instruction, because this will lead to incorrect results. 3. Branching: In order to fetch and execute the next instruction, we must know what that instruction is. If the present instruction is a conditional branch, and its result will lead us to the next instruction, then the next instruction may not be known until the current one is processed. 4. Interrupts: Interrupts set unwanted instruction into the instruction stream. Interrupts effect the execution of instruction. 5. Data Dependency: It arises when an instruction depends upon the result of a previous instruction but this result is not yet available.

18. Advantages of Pipelining The cycle time of the processor is reduced. It increases the throughput of the system It makes the system reliable. Disadvantages of Pipelining The design of pipelined processor is complex and costly to manufacture. The instruction latency is more.

19. Vector(Array) Processor and its Types Array processors are also known as multiprocessors or vector processors. They perform computations on large arrays of data. Thus, they are used to improve the performance of the computer. Types of Array Processors There are basically two types of array processors: Attached Array Processors SIMD Array Processors Attached Array Processors An attached array processor is a processor which is attached to a general purpose computer and its purpose is to enhance and improve the performance of that computer in numerical computational tasks. It achieves high performance by means of parallel processing with multiple functional units.

21. SIMD Array Processors SIMD is the organization of a single computer containing multiple processors operating in parallel. The processing units are made to operate under the control of a common control unit, thus providing a single instruction stream and multiple data streams. A general block diagram of an array processor is shown below. It contains a set of identical processing elements (PE's), each of which is having a local memory M. Each processor element includes an ALUand registers. The master control unit controls all the operations of the processor elements. It also decodes the instructions and determines how the instruction is to be executed. The main memory is used for storing the program. The control unit is responsible for fetching the instructions. Vector instructions are send to all PE's simultaneously and results are returned to the memory. The best known SIMD array processor is the ILLIAC IV computer developed by the Burroughs corps. SIMD processors are highly specialized computers. They are only suitable for numerical problems that can be expressed in vector or matrix form and they are not suitable for other types of computations.

23. Why use the Array Processor Array processors increases the overall instruction processing speed. As most of the Array processors operates asynchronously from the host CPU, hence it improves the overall capacity of the system. Array Processors has its own local memory, hence providing extra memory for systems with low memory.

24. Vector processing Processing of sequences of data in a uniform manner, a common occurrence in manipulation of matrices (whose elements are vectors) or other arrays of data. A vector processor will process sequences of input data as a result of obeying a single vector instruction and generate a result data sequence. This orderly progression of data can capitalize on the use of pipeline processing. Application Area of Vector processing: Long Range weather forecasting Petroleum explorations Data Analysis Medical Diagnosis Space Flight Simulation AT& Expert system Image Processing