Presentation is loading. Please wait.

Presentation is loading. Please wait.

Tutorials #4-#5 Coltroller + dataPath design

Published byCoskun Jamaković Modified over 5 years ago

Similar presentations

Presentation on theme: "Tutorials #4-#5 Coltroller + dataPath design"— Presentation transcript:

1 Tutorials #4-#5 Coltroller + dataPath design
234262 Tutorials #4-#5 Coltroller + dataPath design – © Yohai Devir 2007 Technion - IIT

2 Computing N! #1 – pseudo-Code i = N; result = 1; while (i != 1) {
result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

3 Computing N! (2) #2 – finding variables i = N; result = 1;
while (i != 1) { result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

4 Computing N! (3) #3 – operations i = N; result = 1; while (i != 1) {
result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

5 Computing N! (4) The universal switch Universal switch i = N;
result = 1; while (i != 1) { result = result * i; i = i - 1; } done = 1; output(result); Universal switch Can connect every output to every input Can produce any fixed number Control signals can resolve any condition in the algorithm Will be implemented later. – © Yohai Devir 2007 Technion - IIT

6 Computing N! (5) The Datapath i = N; result = 1; while (i != 1) {
result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

7 Computing N! (5) The Datapath i = N; result = 1; while (i != 1) {
result = result * i; i = i - 1; } done = 1; output(result); N – © Yohai Devir 2007 Technion - IIT

8 Computing N! (5) The Datapath i = N; result = 1; while (i != 1) {
result = result * i; i = i - 1; } done = 1; output(result); 1 – © Yohai Devir 2007 Technion - IIT

9 Computing N! (6) Datapath Flow Chart – what operations can be done in parallel ? A = B + C D = A + C i = N; result = 1; while (i != 1) { result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

10 Computing N! (6) Datapath Flow Chart – what operations can be done in parallel ? i = N; result = 1; while (i != 1) { result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

11 Computing N! (6) Datapath Flow Chart – what operations can be done in parallel ? i = N; result = 1; while (i != 1) { result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

12 Computing N! (6) Datapath Flow Chart – what operations can be done in parallel ? i = N; result = 1; while (i != 1) { result = result * i; i = i - 1; } done = 1; output(result); – © Yohai Devir 2007 Technion - IIT

13 Computing N! (7) Datapath – implementing the switch
– © Yohai Devir 2007 Technion - IIT

14 Computing N! (8) CONTROL – flow chart 234262 – © Yohai Devir 2007
Technion - IIT

15 Computing N! (8) CONTROL – flow chart 234262 – © Yohai Devir 2007
Technion - IIT

16 Computing N! (8) CONTROL – flow chart 234262 – © Yohai Devir 2007
Technion - IIT

17 Computing N! (8) CONTROL – flow chart 234262 – © Yohai Devir 2007
Technion - IIT

18 Computing N! (8) CONTROL – flow chart 234262 – © Yohai Devir 2007
Technion - IIT

19 Computing N! (9) CONTROL – implementation 234262 – © Yohai Devir 2007
Technion - IIT

20 Computing N! (9) CONTROL – implementation CS 00 1 01 10 11
Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 – © Yohai Devir 2007 Technion - IIT

21 Computing N! (10) CONTROL + DP 234262 – © Yohai Devir 2007
Technion - IIT

22 Computing N! (10) – © Yohai Devir 2007 Technion - IIT

23 DP signals Control signals Comment 1 3 ? 00 2 4 5 6 7 8 N i res i-1
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 2 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

24 DP signals Control signals Comment 1 3 ? 00 2 4 5 6 7 8 N i res i-1
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 2 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

25 DP signals Control signals Comment 1 3 ? 00 2 4 5 6 7 8 N i res i-1
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 iN; res 1 2 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

26 DP signals Control signals Comment 1 3 ? 00 01 2 4 5 6 7 8 N i res i-1
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

27 DP signals Control signals Comment 1 3 ? 00 01 2 4 5 6 7 8 N i res i-1
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

28 DP signals Control signals Comment 1 3 ? 00 01 2 4 5 6 7 8 N i res i-1
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

29 DP signals Control signals Comment 1 3 ? 00 01 2 i=1? 4 5 6 7 8 N i
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 i=1? 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

30 DP signals Control signals Comment 1 3 ? 00 01 2 Ø i=1? 4 5 6 7 8 N i
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 Ø i=1? 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

31 DP signals Control signals Comment 1 3 ? 00 01 2 Ø i=1? 4 5 6 7 8 N i
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 Ø i=1? 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

32 DP signals Control signals Comment 1 3 ? 00 01 2 Ø 10 i=1? 4 5 6 7 8 N
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 Ø 10 i=1? 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

33 DP signals Control signals Comment 1 3 ? 00 01 2 Ø 10 i=1? 4 5 6 7 8 N
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 Ø 10 i=1? 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

34 DP signals Control signals Comment 1 3 ? 00 01 2 Ø 10 i=1? 4 5 6 7 8 N
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 Ø 10 i=1? resi*res ii-1 4 5 6 7 8 – © Yohai Devir 2007 Technion - IIT

35 DP signals Control signals Comment 1 3 ? 00 01 2 Ø 10 i=1? 4 6 5 11 7
CS Sel_i Load_i Sel_res Load_res Done 00 1 01 10 11 DP signals Control signals Comment N i res i-1 i*res zero CS NS seli selres loadi loadres done 1 3 ? 00 01 iN; res 1 2 Ø 10 i=1? resi*res ii-1 4 6 5 11 7 8 – © Yohai Devir 2007 Technion - IIT

36 Another example – © Yohai Devir 2007 Technion - IIT

37 2nd example - hardware i = N; K = 2; while (i / K >= K) {
If (i % K == 0) { i = i + 1; } else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

38 2nd example - hardware i = N; K = 2; while (i / K >= K) {
If (i % K == 0) { i = i + 1; } else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

39 2nd example - hardware i = N; K = 2; while (i / K >= K) {
If (i % K == 0) { i = i + 1; } else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

40 i = N; K = 2; while (i / K >= K) { If (i % K == 0) { i = i + 1;
} else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

41 i = N; K = 2; while (i / K >= K) { If (i % K == 0) { i = i + 1;
} else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

42 i = N; K = 2; while (i / K >= K) { If (i % K == 0) { i = i + 1;
} else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

43 i = N; K = 2; while (i / K >= K) { If (i % K == 0) { i = i + 1;
} else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

44 i = N; K = 2; while (i / K >= K) { If (i % K == 0) { i = i + 1;
} else { K = K + 1; } done = 1; output (i); – © Yohai Devir 2007 Technion - IIT

45 – © Yohai Devir 2007 Technion - IIT

46 – © Yohai Devir 2007 Technion - IIT

Download ppt "Tutorials #4-#5 Coltroller + dataPath design"

Similar presentations

1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.

1 The 2-to-4 decoder is a block which decodes the 2-bit binary inputs and produces four output All but one outputs are zero One output corresponding to.
CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.

CS 140 Lecture 16 System Designs Professor CK Cheng CSE Dept. UC San Diego 1.
Exercise (1).

Exercise (1).
Multiplication and Division

Multiplication and Division
1 (Review of Prerequisite Material). Processes are an abstraction of the operation of computers. So, to understand operating systems, one must have a.

1 (Review of Prerequisite Material). Processes are an abstraction of the operation of computers. So, to understand operating systems, one must have a.
234262 – © Yohai Devir 2007 Technion - IIT 234262 Tutorial #10 MIPS commands.

– © Yohai Devir 2007 Technion - IIT Tutorial #10 MIPS commands.
Revision.

Revision.
Order Analysis of Algorithms Debdeep Mukhopadhyay IIT Madras.

Order Analysis of Algorithms Debdeep Mukhopadhyay IIT Madras.
Give qualifications of instructors: DAP

Give qualifications of instructors: DAP
PSEUDOCODE & FLOW CHART

PSEUDOCODE & FLOW CHART
Put your group member’s name here, click on View -> Master -> Slide Master. ECE 408/CS483, University of Illinois, Urbana-Champaign Title Member Names.

Put your group member’s name here, click on View -> Master -> Slide Master. ECE 408/CS483, University of Illinois, Urbana-Champaign Title Member Names.
Figure 1.1 Basic components of a simple computer system © 2003 Brooks/Cole Publishing / Thomson Learning™

Figure 1.1 Basic components of a simple computer system © 2003 Brooks/Cole Publishing / Thomson Learning™
CS 151 Digital Systems Design Lecture 37 Register Transfer Level

CS 151 Digital Systems Design Lecture 37 Register Transfer Level
Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.
CS 140 Lecture 17 Professor CK Cheng 11/26/02. System Designs 1.Intro 2.Spec 3.Implementation.

CS 140 Lecture 17 Professor CK Cheng 11/26/02. System Designs 1.Intro 2.Spec 3.Implementation.
234262 Tutorial #6 Controller + DataPath part II 234262 – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.

Tutorial #6 Controller + DataPath part II – © Yohai Devir 2007 © Dima Elenbogen 2009 Technion - IIT.
Algorithm Design CS105. Problem Solving Algorithm: set of unambiguous instructions to solve a problem – Breaking down a problem into a set of sub- problems.

Algorithm Design CS105. Problem Solving Algorithm: set of unambiguous instructions to solve a problem – Breaking down a problem into a set of sub- problems.
234262 – © Yohai Devir 2007 Technion - IIT 234262 Tutorial #6 Controller + DataPath part II.

– © Yohai Devir 2007 Technion - IIT Tutorial #6 Controller + DataPath part II.
Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Written by: Haim Natan Benny Pano Supervisor:

Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab Written by: Haim Natan Benny Pano Supervisor:
234262 Tutorials #4-#5 Controller + DataPath design 234262 – © Yohai Devir 2007 Technion - IIT.

Tutorials #4-#5 Controller + DataPath design – © Yohai Devir 2007 Technion - IIT.

Similar presentations

Ads by Google