1. Single Link FPGA DAC38J84 ~sync Link0
The physical driver of the ~sync signal can be SYNCB (LVDS), SYNC_N_AB, or SYNC_N_CD. The JESD204B standard specified LVDS type driver, but the user may use standard CMOS driver for ~sync carrier. The user will need to program config97 accordingly based on the physical driver selection.
~sync
FPGA
DAC38J84
RX_0
RX_1 .
RX_N-1
RX_N
Link0
The number of SERDES lane used for the DAC38J84 is aggregated into a single link (link0).
Configured in config73.

2. Dual Link FPGA 0 Dual FPGA setup with one single DAC38J84 DAC38J84
The physical driver of the ~sync signal can be SYNCB (LVDS), SYNC_N_AB, or SYNC_N_CD. The JESD204B standard specified LVDS type driver, but the user may use standard CMOS driver for ~sync carrier. The user will need to program config97 accordingly based on the physical driver selection (select Link0).
The number of SERDES lane used for the DAC38J84 is aggregated into a single link (link0).
Configured in config73.
Link0
~sync_0
FPGA 0
DAC38J84
RX_0 .
Dual FPGA setup with one single DAC38J84
RX_1
~sync_1
FPGA 1
RX_N-1 .
RX_N
Link1
The number of SERDES lane used for the DAC38J84 is aggregated into a single link (link1).
Configured in config73.
Select Link1 in config97