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Implementing Logic Gates and Circuits
Discussion D3.3
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Implementing Logic Gates and Circuits
Logic With Relays Integrated Circuit Implementation of Gates Transistor-Transistor Logic (TTL) Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)
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Relays A A C C B B Normally Open Relay Normally Closed Relay
A-B closed when C = 1 (current through coil) A-B open when C = 1 (current through coil)
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NOT Gate 5V X Y 1 closed open X Y 1
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NOT Gate 5V X Y 1 closed open X Y 1
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AND Gate X Y Z 5V X Y Z X Y Z
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AND Gate X Y Z 5V X Y Z X Y Z
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AND Gate X Y Z 1 X Y Z
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AND Gate 1 X Y Z X Y Z
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AND Gate 1 X Y Z 1 X Y Z
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OR Gate 5V X Y Z X Y Z X Y Z
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OR Gate 5V X Y Z X Y Z X Y Z
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OR Gate X Y Z X Y Z 1
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OR Gate X Y Z X Y Z 1
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OR Gate X Y Z X Y Z 1 1
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Implementing Gates Using MOSFET Integrated Circuits
Relays A A A C C C B B B nMOS transistor A-B closed when C = 1 (normally open) pMOS transistor A-B closed when C = 0 (normally closed) Normally open Normally closed
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NOT Gate 5V X Y X Y Y = X' X Y 1
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NOT Gate 5V X Y X Y 1 Y = X' X Y 1
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NOT Gate 5V X Y X Y 1 Y = X' X Y 1
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NAND Gate 5V Z X Z Y X X Y Z Y
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NAND Gate 5V Z X Z Y X X Y Z Y
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NAND Gate 5V Z X Z Y X X Y Z 1 Y
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NAND Gate 5V Z X Z 1 Y X X Y Z Y
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NAND Gate 5V Z X Z 1 Y X X Y Z 1 Y
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NOR Gate 5V X X Z Y Y Z X Y Z
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NOR Gate 5V X X Z Y Y Z X Y Z
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NOR Gate 5V X X Z Y 1 Y Z X Y Z
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NOR Gate 5V 1 X X Z Y Y Z X Y Z
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NOR Gate 5V 1 X X Z Y 1 Y Z X Y Z
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AND Gate 5V Z 5V X Y NAND-NOT
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OR Gate 5V NOR-NOT X Z 5V Y
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Transmission Gate (TG)
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Selector and Exclusive- OR Constructed with Transmission Gates
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Transistor-Transistor Logic (TTL)
Developed in mid-1960s Large family (74xx) of chips from basic gates to arithmetic logic units Becoming obsolete with the development of programmable logic devices (PLDs)
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TTL Chips
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TTL NAND, NOR, XOR
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TTL Multiple-input Gates
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Small-Scale Integrated (SSI) Circuits
1 to 10 gates NAND gate has 4 transistors
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Medium-Scale Integrated (MSI) Circuits
gates Adders Comparators Multiplexers Decoders
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Large-Scale Integrated (LSI) Circuits
gates Arithmetic Logic Units
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Very-Large-Scale Integrated (VLSI) Circuits
>1000 gates Microprocessors Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)
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Basic PLD Structure
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Alternate PLD Representation
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PLD Connections for XOR
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1975 – Signetics invents the FPLA
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1978 – MMI introduces the PAL
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1983 – AMD introduces the 22V10 1984 – Lattice introduces the GAL – an electrically erasable PAL
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The GAL 16V8 1 2 3 4 5 6 7 9 10 11 12 8 19 20 17 18 15 16 13 14 GND Vcc I/CLK I I/O I/OE GAL 16V8
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Structure of the GAL 16V8 PLD
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GAL 16V8 Input Buffer
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Structure of the GAL 16V8 PLD
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GAL 16V8 Polarity Control X X OE A C Pin B Polarity
closed B = C = A open B = 1 C = A'
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Structure of the GAL 16V8 PLD
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Programming Controller
XC CPLDs Function Block 1 JTAG Controller Block 2 I/O Block 4 3 Global Tri-States 2 or 4 Block 3 In-System Programming Controller FastCONNECT Switch Matrix JTAG Port Global Set/Reset Global Clocks Blocks 1 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin-locking architecture 10,000 program/erase cycles Complete IEEE JTAG capability
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XC9500 Function Block Each function block is like a 36V18 ! To
FastCONNECT From 2 or 4 3 Global Tri-State Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !
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XC9500 Product Family 9536 9572 95108 95144 95216 95288 Macrocells 36
Usable Gates 800 1600 2400 3200 4800 6400 tPD (ns) 5 7.5 7.5 7.5 10 10 Registers 36 72 108 144 216 288 Max I/O 34 72 108 133 166 192 Packages VQ44 PC44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 HQ208 BG352 PQ160 HQ208 BG352
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Xilinx 95108 6 function blocks Each contains 18 macro cells
Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs
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Architecture of the Xilinx XC95108 CPLD
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PLDT-3 Buttons Xilinx XC95108 CPLD 7 segment display Switches LEDs
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PLDT-3 12 macro cells connected to I/O pins 4 pushbuttons
8 toggle switches 8 dip switches 16 LEDs 2 7-segment displays On-board clock signals (4 MHz and 1 Hz)
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Field Programmable Gate Arrays
FPGAs Field Programmable Gate Arrays
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1985 – Xilinx introduces the LCA (Logic Cell Array)
The Xilinx XC3000 CLB (configurable logic block).
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1991 – Xilinx introduces the XC4000 Architecture
Programmable Interconnect I/O Blocks (IOBs) XC4003 contained 440,000 transistors 0.7-micron process Configurable Logic Blocks (CLBs)
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XC4000E/X Configurable Logic Blocks
D Q SD RD EC S/R Control 1 F' G' H' DIN H Func. Gen. G F G4 G3 G2 G1 F4 F3 F2 F1 C4 C1 C2 C3 K YQ Y XQ X H1 DIN S/R EC 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset
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Look Up Tables Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: Look Up Table 4-bit address Combinatorial Logic A B C D Z A B C D Z 4 (2 ) 2 = 64K ! Capacity is limited by number of inputs, not complexity Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM G Func. Gen. G4 G3 G2 G1 WE
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What’s Really In that Chip?
Programmable Interconnect Points, PIPs (White) Switch Matrix Routed Wires (Blue) Direct Interconnect (Green) CLB (Red) Long Lines (Purple)
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1998 – Xilinx introduces the Virtex®™ FPGA family
0.25-micron process
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2003 – Xilinx introduces the Spartan®™-3 family of products
Very low cost World’s first 90 nm FPGA
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Block diagram of Xilinx Spartan IIE FPGA
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Each Spartan IIE CLB contains two of these CLB slices
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Block diagram of Xilinx Spartan-3 FPGA
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Each Spartan-3 CLB contains four CLB slices
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Spartan 3 Board
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CPLDs vs. FPGAs
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Xilinx will release the world’s first
one-billion transistor device this year x
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