1. Will Machine Learning & Robotics Dominate Tomorrow's Chip Design Process?
Opening comments…
KT Moore
Vice President, Cadence Digital & Signoff Group
May 13, 2019

2. Robotics in Chip Design Process Today
Process Control
Quality Control
Clean Transport
Wafer Testing
Robotics play a key role in facilitating production of electronics and semiconductors.
Six-axis articulation in conjunction with high speed is an important trend in the small part electronics industry.
Robotic assembly of connectors is a growing trend. This application requires precision and tolerance because of so many small parts. 
Moving silicon wafers at high speeds without causing damage is a fundamental task robots are increasingly called on to perform
Chip Packaging
PCB Assembly
Wafer Inspection

3. Robotics in Chip Design Process Today
Process Control
Quality Control
Clean Transport
Wafer Testing
Robotics play a key role in facilitating production of electronics and semiconductors.
Six-axis articulation in conjunction with high speed is an important trend in the small part electronics industry.
Robotic assembly of connectors is a growing trend. This application requires precision and tolerance because of so many small parts. 
Moving silicon wafers at high speeds without causing damage is a fundamental task robots are increasingly called on to perform
Chip Packaging
PCB Assembly
Wafer Inspection

4. Next Generation Robotics Will Have More Intelligence
And this is where ML comes in

5. Machine Learning Is Not New…
60 Years of Research
Machine Learning is the field of study that gives computers the ability to learn without being explicitly programmed.”
Artificial Intelligence
Neural Networks
Machine Learning and Neural Networks have been a research topic without good practical applications for as long as computers have been around. As compute capacity rapidly increased, researchers were finding that following developed methods but using more compute brute force were yielding dramatically improved results. Deep Learning is loosely defined as a NN with > 4 stages. Around 2010, researchers were delivering practical applications by leveraging graphics processors as NN training accelerators. As new ML applications have deployed, investment has gone into supporting the infrastructure. For example, NVDA, MSFT, IBM, and Amazon all offer specialized machine learning accelerators as part of their cloud offering today.
Big Data
High-Performance Cloud
Massive Storage
Massively Parallel +
CNN
Deep Learning
Arthur Samuel, 1959

6. Driven By More and More Data
Internet of Things
Datacenter, Servers,
In-Memory, and Big Data
DATA
CREATION
DATA
PROCESSING AI
DATA
TRANS-
MISSION
DATA
STORAGE
I’ve said this before - I strongly believe that it’s a data driven world and everything is about data – creation, processing, transmission and storage. All requires power efficient computing, low latency and high bandwidth transmission and high density storage. And at the center of it all is AI / ML
HDD
DRAM
NAND
Wireless and Wired Infrastructure
Source: Credit Suisse / Cadence

7. Driving Overall Semiconductor Growth
Source: Barclay
Significant Growth Projected

8. AI – Key Semiconductor Driver
AI semi expected to grow more than
3X total semi market
AI Semi Spend
Smartphone Semi Spend
The result of these AI trends will be substantial for semiconductors. While other applications will continue to grow, there is predicted substantial growth in AI applications for semiconductors.
Semiconductor Revenues Over Time ($B)
Source: IBS

9. Across Every Industry Segment
Video
Gaming/AR/VR
Across Every Industry Segment
IoT
Medical
71% CAGR
Automotive
Data in Exabytes (1018)
Robotics
2018
2019
2020
2021
2022
2023
Video
Gaming
IoT
AR / VR
Medical
Robotics
Auto
Explosion of data happening for all application domains - video is by far the largest contributor as you can see. Need to filter this data to identify most relevant portions for effective decision making and actions – this is where ML will greatly help
Source: IBS
System Design
Advanced Packaging
Complex PCB and Chassis
System Analysis
ML / AI

10. Cadence System Design Enablement – Intelligent System Design
Mobile
Cloud / Datacenter
Automotive
Aero and Defense
Medical
Industrial
Pervasive Intelligence
Machine Learning Applications — Machine Learning Embedded Systems
System Innovation
System Design and Analysis — Device/Software Design — Embedded Security and Safety
Design Excellence
Full-Flow Digital — Analog and RF — Verification — Interface and Processor IP
Cloud Enabled — Partnerships with Ecosystem Leaders
Cloud

11. Design Excellence EDA Foundation
Engine Performance
Compute Capacity
Smart Flows
Numerical Solvers
Single CPU Performance
Efficient Memory Management
Signoff Accuracy
Multi-Threaded
Fully Distributed
Shared Memory and Storage
Cloud Ready
Natively Shared Engines
PPA Excellence
Digital Full Flow
Verification Suite
Chip, Package and Board
Optimizing PPA, reducing time-to-market, enabling high quality results

12. Design Excellence: Cadence’s Comprehensive Portfolio
Custom IC, IC Packaging & PCB
Digital & Signoff IP
Verification

13. World-Class PPA Results with Cadence Digital Full Flow
Cadence Leadership in Digital
Best-in-class PPA leadership
Concurrent power, performance, and area (PPA) optimization
Shared placement, routing, extraction, delay calculation
Industry’s first integrated STA and EMIR signoff solution
Fully integrated and massively parallel full flow
Core engines for all tools threaded and distributed
Multi-CPU and multi-machine parallel architecture
Integrated in-design signoff and ECO
Accelerating market adoption
Full flow delivers 20% better PPA with fastest TAT
Digital tools deployed at 17 of top 20
Used on more than nm tapeouts
Stratus™ Synthesis
Modus DFT Software
Design
Creation
Genus™ RTL Synthesis
Joules™ RTL Power
Conformal® LEC, ECO, LP
Innovus™ Implementation System
Implementation
Design
Tempus™ Signoff STA
Voltus™ Signoff Power
Signoff
Quantus™ Signoff Extraction
Pegasus™ DRC, LVS, DFM
Liberate™ Characterization
Production Deployment in 17 of Top 20
Integrated Product Portfolio

14. Machine Learning at Cadence
Inside
Better PPA, faster engines
Improved testing / diagnostics
Outside
Automated design flow
Productivity improvement
Enablement
Hardware / software co-design
Tensilica® IP for machine learning

15. Machine Learning Technology Inside Digital Flow
Physical Design
Signoff Timing + EMIR
Signoff Timing
Formal Verification
Innovus™ ML Option
“Tempus Power Integrity”
Tempus – PBA
Conformal Smart LEC

16. Innovus Machine Learning P&R Results
Designs with the same library and delay settings
7nm CPU Results
Multiple training runs
Innovus Run 1
Innovus Run 2
Innovus Run 3
Metric
Reference
ML Result
Impact
TNS
-8.356
53.2%
WNS
-0.052
-0.043
17.3%
Leakage
253.08
7.3%
Total Power
2.6%
Machine Learning
Inference Model
Machine Learning
Inference Model
Machine Learning
Inference Model
Training takes 4-5 hours per design using conventional CPUs
Can get 2-3X faster using GPU
Innovus Machine Learning Training
Innovus™ PPA Improves with Each Run

17. AI and Machine Learning: Core EDA Genus and Innovus digital full flow
Genus and Innovus Full Flow
Genus and Innovus ML Results
Design
Input
Genus™
Innovus™
Tempus™
Auto-detects SI-critical region
Auto-detects high congestion
Add routing screen
Knowledge Graph + Machine Learning
TNS Improvements
Result
Optimized PPA
Design
Baseline
Final
Gain
7nm CPU
-123ns
-105ns
14%
16nm SoC
-1499ns
-1184ns
21%

18. Summary
Use of Robotics and Machine Learning is increasing in the design and manufacturing of semiconductors
Machine Learning will drive more Robotic automation is the chip design process.
Machine Learning is required to EDA design flows deliver best silicon Power, Performance, and Area