1. FPGA’s
9/22/08

2. Basic types of FPGA’s One time programmable
Reprogrammable (non-volatile)
Retains program when powered down
SRAM-based reprogramable
Must be reprogrammed each time powered up
Xilinx Spartan 3E

3. Spartan-3E Architecture Fundamental Elements
Configurable Logic Blocks (CLBs)
Consists of RAM based look up table to implement logic and storage elements that can be used as flip-flops or latches.
Input Output Blocks (IOBs)
Controls the flow of data between IO pins and internal logic. Supports many different signal standards. (Tri-state, bidirectional, LVTTL, etc.
Block RAM (BRAM) – 18 Kbit dual ported RAM
18 bit Multiplier Blocks
Digital Clock Manager (DCM)

4. • Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
• Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

5. CLB’s

8. Spartan 3E IO Blocks (IOB’s)
IOB’s control flow of data between IO pins and the internal logic.
Each IOB supports bidirectional data flow, 3-state operation, and numerious different signal standards. (We will typically use LVTTL). See data sheet.

9. I/O block

10. I/O block continued

11. CLB’s – four slices per CLB

12. Spartan 3 Configurable Logic Blocks (CLB’s)
CLBs contain Ram based lookup tables to implement logic and storage elements that can be used as flip-flops or latches.
CLBs can be programmed to perform a wide variety of logic functions as well as store data.

13. Top slice of CLB