1. TCL Script and HLS Batch mode results of Cluster Finder Algorithm

2. TCL script to run HLS in Batch mode
TCL script to run HLS in normal mode
###########################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) Xilinx, Inc. All Rights Reserved.
open_project Cluster
set_top getClustersInCard
add_files Cluster/ClusterFinder.cc
add_files Cluster/ClusterFinder.hh
add_files -tb Cluster/testClusterFinder.cc
open_solution "solution1"
set_part {xcku025-ffva c} -tool vivado
create_clock -period name default
#source "./Cluster/solution1/directives.tcl"
csim_design -setup
csynth_design
cosim_design
export_design -format ip_catalog
############################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) Xilinx, Inc. All Rights Reserved.
open_project Cluster_batch_four
set_top getClustersInCard
add_files Cluster/ClusterFinder.cc
add_files Cluster/ClusterFinder.hh
add_files -tb Cluster/testClusterFinder.cc
set all_solution [list sol1 sol2 sol3]
set all_part [list xcku025-ffva c xcku035-ffva e xc7k160tfbg676-3]
foreach solution $all_solution part $all_part {
#solutions
open_solution -reset $solution
set_part $part -tool vivado
create_clock -period name default
source "./Cluster/solution1/directives.tcl"
csim_design
csynth_design
#cosim_design
export_design }
exit

3. TCL script to run HLS in Batch mode (Ultrascale FPGA)
############################################################
## This file is generated automatically by Vivado HLS.
## Please DO NOT edit it.
## Copyright (C) Xilinx, Inc. All Rights Reserved.
open_project Cluster_batch_ultrascale
set_top getClustersInCard
add_files Cluster/ClusterFinder.cc
add_files Cluster/ClusterFinder.hh
add_files -tb Cluster/testClusterFinder.cc
set all_solution [list sol1 sol2 sol3 sol4 sol5 sol6]
set all_part [list xcku115-flvf c xcku115-flvf i xcku115-flvf e xcvu440-flgb c xcvu440-flgb i xcvu440-flgb e]
foreach solution $all_solution part $all_part {
#solutions
open_solution -reset $solution
set_part $part -tool vivado
create_clock -period name default
source "./Cluster/solution1/directives.tcl"
csim_design
csynth_design
#cosim_design
#export_design }
exit

4. Kintex Ultrascale
Virtex Ultrascale
sol1: xcku115-flvf c sol2: xcku115-flvf i sol3: xcku115-flvf e
sol4: xcvu440-flgb c sol5: xcvu440-flgb i sol6: xcvu440-flgb e

5. Kintex 7
Virtex 7
sol1: xc7k410tffv900-1 sol2: xc7k410tffv900-2 sol3: xc7k410tffv900-3
sol4: xq7vx980trf1930-2l sol5: xq7vx980trf1930-1i

6. Further :
1. Kintex Ultrascale+
2. Virtex Ultrascale+
3. Cluster Track Linker On all described FPGAs