1. SP Main FPGA & DT transition card design status
Alex Madorsky UF
08/21/03

2. SP Main FPGA design status
Mezzanine card with FPGA works
Firmware downloading:
Little troubles related to Xilinx ISE 5.2 software version
Workaround available, Xilinx contacted
Internal bus interface under design:
Designed separately from main SP logic for faster compilaton
Done so far:
R/W access to one internal register
Priorities for test with DT (will be finished in a few days):
Read/write access to LUT memory
Input FIFOs for DT data
Other priorities
Compile with full SP logic
Test FIFOs for SP logic
Test software for SP logic
My talk is devoted to UF/PNPI design features and solutions for CMS EMU HV system. I will introduce to you the main design approaches and important technical details. The subjects for discussion will be:
HV regulator
Current sensor
Fuse control operation
Digital control interface
New mechanical construction
Rice, August 2003
Alex Madorsky

3. DT transition card DT transition card: DT-to-SP cables:
Routing completed (V. Golovtsov)
Board is sent for production, expected next week
Components bought
DT-to-SP cables:
Connectors received
Cable delivery delayed by manufacturer (Belden) till mid-September
Rice, August 2003
Alex Madorsky