1. EGR 2131 Unit 4 CAD Tools and VHDL
Read Brown & Vranesic, Sections 2.9 to 2.12 and Sections A.1 to A.4.
Homework #4 and Lab #4 due next week.
Quiz next week.
-Do Quiz #3.
Handouts: Unit 4 Practice Sheets;

2. Fixed-Function Chips Versus Programmable Chips
The chips in the 7400 series are called fixed-function chips because the gates are permanently configured in a certain way when the chip is manufactured.
Until the 1990’s, such chips were used in the design of new products.
Today, programmable chips have replaced fixed-function chips in new designs.

3. Fixed-Function Chips Versus Programmable Chips (Cont’d.)
Advantages of programmable chips over fixed-function chips include:
Reduced complexity of circuit boards
Lower power requirements
Less board space
Simpler testing procedures
Higher reliability
Design flexibility: chip can be reprogrammed to function differently.

4. CAD Tools for Programmable Logic
CAD stands for “computer-aided design.” CAD tools are software programs that engineers use in designing systems.
The CAD tools that interest us are software provided by manufacturers of programmable chips that let us program their chips.
In particular, we’ll use the Quartus II software provided by Altera (now part of Intel).

5. Overview of the Design Process Using CAD Tools
We can enter the design in one of two ways:
Schematic capture
Text entry using a hardware description language (HDL), such as VHDL.

6. Schematic Capture
In schematic capture, the design is drawn on a computer screen by placing components and connecting them with wires.

7. Choices in Quartus
In Quartus you can place gates either using generic names (such as AND2) or using the number of a 74XX-series chip.
To use the latter, you must know the 74XX number for the chip you want. Some examples are listed here.
Wikipedia has a complete list of 74XX chips (not all of which are available in Quartus.)
Type
Sample Chips
2-input NAND
7400
2-input AND
7408
2-input OR
7432
3-input AND
7411 7

8. Choices in Quartus (Cont’d.)
Generic:
74XX: 8

9. Text Entry
In text entry, the design is typed as a sequence of commands from a hardware description language (HDL).
Learning an HDL takes longer than learning to do schematic entry. But for complex designs it is much more powerful and simpler.

10. Some Popular Hardware Description Languages
Open-standard HDLs
VHDL (IEEE 1076)
Verilog (IEEE 1364)
Proprietary HDLs
CUPL
ABEL (Advanced Boolean Expression Language, now owned by Xilinx)
AHDL (Altera HDL)
In this course we’ll use VHDL!

11. A VHDL Sample
A VHDL design is divided into an entity (which lists the design’s inputs and outputs) and an architecture (which describes the design’s logic).
Here’s a simple example:
ENTITY example IS PORT (x1, x2, x3: IN BIT; f: OUT BIT); END example;
ARCHITECTURE logicfunction OF example IS BEGIN f <= (x1 OR x2) AND x3; END logicfunction;

12. Functional Simulation
After entering your design, you’ll simulate it in software to verify its operation. In this course, our simulations will use timing diagrams to show what output the design produces for specified inputs.

13. Chip Configuration (Device Programming)
After simulating your design, you’ll download the design from your computer to your target device (chip) and test it in hardware.
We’ll use this Altera DE2-115 board. It has an Altera Cyclone IV programmable chip, along with switches, LEDs and many other I/O devices for testing your design after you’ve downloaded it to the chip.

14. Our Software and Equipment
Software: Altera’s Quartus II, version 13.0 sp1. (Free download, so you can install it at home.)
Hardware: Altera Cyclone IV chip mounted on Terasic’s DE2-115 experimenter’s board. (Manual on Intel’s website.)
-Open project BooleanSchematic. Show them .bdf, .vwf, and simulate.
-Show them board, switches, LEDs.

15. VHDL versus a Programming Language
VHDL code looks much like code written in a programming language such as C.
If you have experience with a programming language, you’ll see similarities.
But be careful, because there are important differences between HDLs and programming languages.
A programming language is a procedural language that you use to specify a step-by-step computational procedure.
An HDL is a description language that describes a hardware structure.

16. VHDL Reserved Words
VHDL defines about 120 reserved words, which have special meaning within the language.
A few examples:
ENTITY
PORT
BEGIN
Many pages on the web have a complete list, such as

17. VHDL Operators
VHDL defines many operators and symbols that have special meaning within the language.
A few examples: **
>
&
Many pages on the web have a complete list, such as

18. VHDL Identifiers
When writing VHDL code you will often have to make up identifiers (names) for things. When doing so you must follow some rules:
Identifiers can contain letters, digits, and the underscore character (_), but no other characters or symbols.
Identifiers must begin with a letter (not a digit or underscore) and cannot end with an underscore.
Identifiers cannot contain consecutive underscores.
Identifiers cannot be the same as any VHDL reserved words.

19. Example VHDL Statement
A VHDL statement typically contains reserved words, operators, and identifiers, and possibly other items as well, such as constants.
Example: out1 <= NOT(in1) WHEN in1 = '0';
Identifiers
Note that some reserved words are also operators.
Reserved words
Constant
Operators

20. Case Insensitivity VHDL is not case sensitive.
For example, number, Number, and NUMBER are all the same identifier.
Another example: when you use the reserved word ENTITY, you can type it as entity, or as Entity, or as entitY, and so on.
Good practice: use uppercase for reserved words and lowercase for identifiers. (Our book does this.)

21. Entity/Architecture Pairs
A VHDL description of a design is organized into entity/architecture pairs.
A given design may be described entirely in one such pair, or may be spread across many such pairs.
On your computer’s disk, each pair may reside in its own file, or you may type many pairs in a single file. These files have names ending in .vhd.

22. Entity versus Architecture
The entity part of a VHDL description identifies the design’s inputs and outputs.
The architecture part tells how the values of the outputs depend on the values of the inputs.
A way to think about this: (from Jan Van der Spiegel’s VHDL Tutorial)

23. Entity Declaration
The general form of an entity declaration (slightly simplified) is:
ENTITY entity_name IS
PORT (signal_names: MODE TYPE;
signal_names: MODE TYPE; …
signal_names: MODE TYPE);
END [ENTITY] [entity_name];
Items in bold uppercase are reserved words that must be typed as shown.
Items in italics are replaced by user-chosen names or options.
Items in square brackets are optional.

24. Entity Declaration: Example
Example from Lab 3:
ENTITY Lab3VHDL IS
PORT (x1, x2, x3, x4: IN BIT;
f: OUT BIT);
END Lab3VHDL;
This entity has five signals named x1, x2, x3, x4, f.
Possible modes are IN, OUT, INOUT, BUFFER.
Possible types are BIT, BIT_VECTOR, INTEGER, STD_LOGIC, STD_LOGIC_VECTOR, and others.

25. Many Different Options for the Architecture Body
Entity declarations (preceding slides) are generally short, and they all look pretty similar.
But architecture bodies (following slides) can be very long, and there is great variation among the kinds of statements you’ll find in them.

26. Architecture Body
The general form of an architecture body (simplified) is:
ARCHITECTURE arc_name OF entity_name IS
[signal declarations;]
[component declarations;]
[constant declarations;]
[other declarations and definitions;]
BEGIN
concurrent statements;
END [ARCHITECTURE] [arc_name];

27. Architecture Body: Example
Example from Lab 3:
ARCHITECTURE arc OF Lab3VHDL IS
BEGIN
f <= (x1 AND x2) OR (NOT x3 AND x4);
END arc;
This architecture body has no declarations, which would appear before the word BEGIN.
And it has only one concurrent statement. This statement is an example of a simple signal assignment, which is the simplest kind. Other kinds of concurrent statements that could appear here:
Conditional signal assignments
Selected signal assignments
GENERATE statements
PROCESS statements

28. Simple Signal Assignment Statement
The general form of a simple signal assignment statement is: signal_name <= expression;
When the statement is executed, the expression on the right is evaluated and the resulting value is assigned to the signal named on the left.
This expression can consist of signal names or constants combined with operators. Recall that you can find a complete list of operators here.

29. Simple Signal Assignment Statement: Example
Example from Lab 3: f <= (x1 AND x2) OR (NOT x3 AND x4);
The parentheses are needed here. In VHDL, AND and OR have the same precedence. If we omit the parentheses, Quartus will give an error, since it won’t know the order in which it should execute the ANDs and OR.
Read this as “f gets (x1 AND x2) OR ….”
Do practice questions 1 and 2.

30. Making Connections to the DE2-115 Board
In Lab 4 you’ll use the o’scope to display a signal being generated on the Altera board.
To do this you must assign the correct pin number in Quartus to send the signal out to a pin on the Altera board’s 14-pin general-purpose I/O connector. Then you must plug in our home-made connector block and use an oscilloscope probe to measure the pin to which you sent your signal.
See next slide for pin numbers.

31. Making Connections to the DE2-115 Board (Cont’d.)
Here are the pin numbers to use when you assign pin numbers in Quartus:
PIN_D9
PIN_E10
PIN_F14
PIN_H14
PIN_H13
PIN_J14
PIN_J10
This one is GROUND.

32. Topics From the Missing Chapter 3
The bookstore’s paperback version of our textbook does not contain Chapter 3 because most of the material in this chapter is not needed in an introductory course like this.
But Chapter 3 does discuss four topics that we need:
7400-series standard chips
Programmable logic devices
Exclusive-OR gates
Fan-out and fan-in
The chapter is 90 pages long, of which we need less than 10 pages.

33. Topic #1 From the Missing Chapter: 7400-series standard chips
We’ve already discussed this: from the 1960’s through 1980’s, many products were designed using fixed-function logic chips from the 7400-series.
Wikipedia’s list of 74XX chips
The chips themselves are obsolete today, but design tools such as Quartus still let you use the corresponding chip numbers in your designs, as we did in Lab 3 with the 7490 counter.

34. Topic #2 From the Missing Chapter: Programmable Logic Devices
Programmable Logic Devices (PLDs) are chips with a large number of gates that can be configured to perform a specific logic function. Major types of PLDs are:
SPLD (Simple PLD): the earliest type of programmable logic, used for smaller circuits with a limited number of gates.
CPLD (Complex PLD): contain multiple SPLD arrays and inter-connection arrays on a single chip.
FPGA (Field Programmable Gate Array): a more flexible arrangement than CPLDs, with much larger capacity.

35. The Big Picture: Partial Hierarchy of Programmable Logic Devices (PLDs)
Simple PLDs (SPLDs)
Programmable Array Logic (PALs)
Generic Array Logic (GALs)
Complex PLDs (CPLDs)
Field Programmable Gate Arrays (FPGAs)

36. Approximate Equivalent Densities
The Lattice GAL22V10 (a popular SPLD) is equivalent to about 500 logic gates.
A typical Altera MAX7000 CPLD is equivalent to about 2500 logic gates.
A typical Altera Cyclone FPGA is equivalent to about 50,000 gates.

37. Major PLD Manufacturers
Three big names in this field are
Xilinx, with 51% of market share
Altera, (purchased by Intel in 2015) with 34%
Lattice, with less than 10%
Market share numbers retrieved from Wikipedia on 9/15/2016.

38. Some Product Lines from Altera and Xilinx
CPLDs: MAX
FPGAs: Cyclone, Arria, Stratix
Programming software: Quartus
Xilinx:
CPLDs: CoolRunner, XC9500
FPGAs: Vertix, Spartan, Kintex, Artix
Programming software: Vivado

39. PALs and GALs
SPLDs contain arrays of gates. Two important kinds of SPLD are PALs (Programmable Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix of conductors connected in rows and columns to AND gates.
x x y y
PALs have a one-time programmable (OTP) array, in which fuses are permanently blown, creating the product terms in an AND array. f
Simplified AND-OR array

40. PALs
PALs are programmed with a specialized programmer that blows selected internal fuse links. After blowing the fuses, the array represents the Boolean logic expression for the desired circuit.
x x y y
Example
What expression is represented by the array? f
Do as practice question 3.
X = AB + AB

41. GALs
The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For this reason, they are useful for new product development (prototyping) and for training purposes.
x x y y
GALs were developed by Lattice Semiconductor. f

42. PALs and GALs
PALs and GALs are often represented by simplified diagrams in which a single line represents multiple gate inputs.
Input buffer
x x y y
Single line with slash indicating multiple AND gate inputs
Fuse blown xy
Do as practice question 4.
xy + xy
Fuse intact xy

43. GAL22V10
The GAL22V10 is a typical SPLD. It has 12 dedicated inputs pins and 10 pins that can be used as inputs or outputs.
Link to datasheet
-This chip contains 5892 reprogrammable fuses.
-Each AND gate has 44 inputs.

44. GAL22V10 Fuse Map (partial)
Each of these
intersections is a fuse.
Each of these
AND gates has 44 inputs.
Input pins.
-This chip contains 5892 reprogrammable fuses.

45. CPLDs
A complex programmable logic device (CPLD) has multiple logic array blocks (LABs), each roughly equivalent to an SPLD. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements.
The PIA is the interconnection between the LABs.

46. FPGAs compared to CPLDs
Based on programmable AND array and fixed OR array.
Based on look-up table (LUT), which is basically a truth table. (Results in higher density.)
Both are programmed using the same software, using either schematic entry or text entry.
-Two different but equivalent ways of specifying a logic function: by drawing schematic diagram with ANDs and ORs, or by giving truth table. CPLD implementation is like the former, while FPGA is like the latter.
-A look-up table is like a memory in which you provide the address and the chip reads out what is stored at that address.

47. Simplified Picture of an FPGA
An FPGA contains a huge number of logic blocks, along with programmable switches that let us connect the output of one logic block to the input of another.
What’s in each of these “logic blocks”?...

48. Simplified Picture of a Logic Block within an FPGA
The heart of each logic block is a look-up table (LUT). Shown here is a 2-input LUT before it has been programmed.
Think of each blue box as a bit of memory that can be programmed to hold either a 0 or a 1.
More realistic LUTs have 4 or more inputs instead of 2.

49. Simplified Picture of a Logic Block within an FPGA (Cont’d.)
Now suppose we wish to program this truth table into our chip.
The Quartus software will program each of the little blue boxes in the LUT so that it now looks like this, implementing our truth table.
Do Practice Question 5.

50. Topic #3 From the Missing Chapter: Exclusive-OR Gates
In Unit 2 we studied five basic logic gates:
Inverter
AND OR
NAND
NOR
There are two more:
XOR
XNOR

51. Inclusive-OR versus Exclusive-OR in the English Language
Suppose you invite me to a party at your house and I ask you if you have any cake or ice cream in your fridge. Assuming you tell the truth, how would you answer in each of the following cases?
Here we’re using OR in the inclusive sense.
Cake
Ice Cream
Your Answer No
Yes

52. Inclusive-OR versus Exclusive-OR in the English Language (Cont’d)
Suppose you’ve taken your child to a birthday party and it’s time for dessert. You say to the kid, “You can have cake or ice cream. Which one do you want?” Which of the following cases are you allowing?
Here you’re using OR in the exclusive sense.
Cake
Ice Cream
Allowed? No
Yes

53. x1 f
The XOR Gate x2
The XOR gate produces a HIGH output only when the inputs are at opposite logic levels. The truth table is x1 x2 f 1
The XOR operation is written as f = x1 x2 + x1 x2. Alternatively, it can be written with a circled plus sign between the variables as f = x1 + x2.

54. The XOR Gate Example waveforms: x1 x2 f
Notice that the XOR gate will produce a HIGH only when exactly one input is HIGH.
Do as Practice Question 6.

55. f x1
The XNOR Gate x2
The XNOR gate produces a HIGH output only when the inputs are at the same logic level. The truth table is x1 x2 f 1
The XNOR operation can be written as f = x1 x2 + x1 x2 or as f = x1 + x2.

56. The XNOR Gate Example waveforms: x1 x2 f
Notice that the XNOR gate will produce a HIGH when both inputs are the same. This makes it useful for comparison functions.
Do as Practice Question 7.

57. More Than Two Inputs?
Most textbooks (including ours) restrict XOR and XNOR gates to having only two inputs.
Similarly, in Quartus you’ll find XOR2 and XNOR2, but not higher-input gates such as XOR3 or XOR4.

58. An Application for XOR: Controlled Inverter
A controlled inverter is a circuit that takes a string of data bits and, depending on the logic level on a control line, either
Leaves the string unchanged or
Inverts each bit in the string
Next slide shows how to build an 8-bit controlled inverter from XOR gates.
We’ll see an application of this in Unit 6.

59. An Application for XOR: Controlled Inverter (Cont’d.)
Do as Practice Questions 8, 9.

60. Topic #4 From the Missing Chapter: Fan-Out and Fan-In
Fan-out means the number of inputs that a given output can drive.
The answer depends on the technical limitations of the chip you’re using. Quartus knows these limitations and behaves accordingly.
How many more gates can I connect to U1’s output?

61. Topic #4 From the Missing Chapter: Fan-Out and Fan-In (Cont’d)
Fan-in is an easier concept: a gate’s fan-in is simply how many inputs it has.
Example: this gate’s fan-in is 2.