1. CS 140L Lecture 6
Professor CK Cheng
11/05/02

2. Lab 3 Finite State Machine
Design Flow
Xilinx Process
Transformation from Mealy to Moore machine
State Assignment
Design Process
State Diagram
Logic Synthesis
Placement & Routing
FPGA
(Graphic I/O)
Mealy
Moore
Verilog, VHDL, ABEL

3. Xilinx Process Project Manager.
New project: Family Spartan, Device S05PC84, Speed 4.
State Diagram (ABEL).
Create Macro Component  State Diagram
Schematic Diagram: Call the component (Either on top or bottom of list).
Synthesis.
CLK
rst Z x
7. Timing Diagram.
8. Check Layout # CLBs (blocks)
CLB

4. 3. Transformation from Mealy to Moore Machine
Moore Machine: y(t) = f(x(t), s(t))
Mealy Machine: y(t) = f(s(t))
s(t+1) = g(x(t), s(t))
x(t)
x(t) C1 C2
y(t) C1 C2
y(t)
CLK
CLK
s(t)
s(t)
Moore Machine
Mealy Machine