1. Circuit Switch Design Principles
IEG4020
Telecommunication Switching and Network Systems
Chapter 2
Circuit Switch Design Principles

2. Fig. 2.1. An N x N switch used to interconnect N inputs and N outputs
Space-Domain Circuit Switching 1 2 N .
Inputs
Outputs
Fig An N x N switch used to interconnect N inputs and N outputs

3. Fig. 2.2. Bar and cross states of 2 x 2 switching elements
Strictly Nonblocking
Bar State
Cross State
Fig Bar and cross states of 2 x 2 switching elements

4. Fig. 2.3. (a) Crossbar switch
Strictly Nonblocking 1 2 3 4
Inputs
Outputs
Connections:
Input 1 to Output 3
Input 2 to Output 4
Fig (a) Crossbar switch

5. Blocking 1 2 3 4 Blocking: Input 2 cannot be connected to output 2
if input 1 is already connected to output 1 1 2 3 4
Fig (b) banyan switch

6. Nonblocking Properties
RNB
WSNB
SNB
RNB — Rearrangeably Nonblocking
WSNB — Wide-sense Nonblocking
SNB — Strictly Nonblocking

7. Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking switch1 2 3 4
Fig (a) A 4 x 4 rearrangeably nonblocking switch

8. Fig. 2.4. (b) a connection request from input 4 to output 1 is blocked
Rearrangements 1 2 3 4
Connection cannot be set up between input 4 and output 1
Fig (b) a connection request from input 4 to output 1 is blocked 1 2 3 4
Connection can now be set up between input 4 and output 1
Fig (c) Same connection request can be satisfied by rearranging the existing connection from input 2 to output 2

9. Two states corresponding to the same mapping :1 2 3 4

10. Complexity of nonblocking switches : How to build large switch from smaller switches?
Problems with two-stage networks : 1 2 m .
(a)
N = mn
# lines = m2n
= mN
Bandwidth expansion factor = m
(b) n

11. Fig. 2.5. (a) An example of one-to-one mapping from input to output1． 2． 3． 4． ．1 ．2 ．3 ．4
Fig (a) An example of one-to-one mapping from input to output

12. Fig. 2.5. (b) Number of crosspoints needed for nonblocking switch
N! mappings
M crosspoints 1 2 N .
Fig (b) Number of crosspoints needed for nonblocking switch

13. Fig. 2.6. A three-stage clos switch architecture
Clos Switching Network
n1 × r2
r1 × r3
r2 × n3 .
(1)
(2)
(r1)
(r2)
(r3)
n1r1 = n3r3 = N for N × N switch
ri — # switch
modules in
column i
n1 — # inputs in
column 1
module
n3 — # outputs in
column 3
Necessary condition for nonblocking:
Fig A three-stage clos switch architecture

14. Fig. 2.7. An example of blocking in a three-stage switch
Key:
Find a commonly accessible middle node from both input and output nodes A F G B 1 2 3 4 5 6 7 8 9 H
A request for connection from input 9 to output 4 is blocked
SA = middle-stage nodes used by A
= { F, G }
SB = middle-stage nodes used by B
= { H }
Fig An example of blocking in a three-stage switch

15. Fig. 2.8. The connection matrix of the three-stage networkB F G H
F,G,H 2 1 A r1 B r2
Stage 1 switch
Stage 3 switch
Fig The connection matrix of the three-stage network

16. Fundamental Conditions
Conditions of a Legitimate connection Matrix :

17. Condition for Strictly Nonblocking

18. Condition for Rearrangeably Nonblocking
Rearrangement
—— Substituting symbols in connection matrix such that
1.) Matrix remains legitimate
2.) An unused symbol in row A and column B can be found

19. Condition for Rearrangeably NonblockingSB ‧D SA ．C

20. . . A’ A B’ B A’’ A’” B” Connection between A and B is blocked
Chain terminates at A” because
Fig (a) A chain of C and D originating from B . A’ A” A
A”’ . B’ B B” C D
A already connected to all middle-stage nodes except D
B already connected to all middle-stage nodes except C
Only links used by connections in the chain are shown
Fig (b) Physical connections corresponding to the chain

21. There should be two end points in a chain
A loop in the chain
D occurs twice in this column, making the matrix illegitimate (i.e. physically impossible in associated switch)
There should be two end points in a chain
Fig Illustration showing loops in chains are not permitted in legitimate connection matrix

22. D can now be put in entry (A, B)
Fig (a) Rearrangement of the chain in Fig. 2.9. . . . A’ . B’ C . A” . . B . A . D . B” .
A”’ .
Fig (b) Corresponding rearrangement of connections

23. . . Fig. 2.12. (a) Two chains, one originates from B, one from AD C . A B
Fig (a) Two chains, one originates from B, one from A D C . A B
This column search ends in C, which is not possible
Start searching from B. Column search always looks for D
Fig (b) Illustration that the two chains cannot be connected

24. How many rearrangements?
A new row/column is covered each time a point is included
(r1 + r3 – 2) other rows and columns
At most (r1 + r3 – 1) rearrangements (loose)
Basic: consider two chains, one originates from row A,
one from column B
Choose the shorter chain for rearrangement
A composite move: a move in chain 1 with a move in chain 2
At most r1 – 2 moves before all rows exhausted
At most r3 – 2 moves before all columns exhausted

25. Benes Switching Network
2 x 2 . 1 2 3 4
N-1 N
Fig Recursive decomposition of a rearrangeably nonblocking network

26. Benes Network - Complexity
Number of 2x2 elements in Benes Network :

27. Benes Network - Structure1 2 3 4 5 6 7 8
Baseline Network
Reverse Baseline Network
Fig An 8x8 Benes Network

28. Baseline and Reverse Baseline Networks

29. Fig. 2.15. Illustration of a looping connection setup algorithm
Looping Algorithm 1 2 3 4 5 6 7 8
Set up paths for input-output pairs :
(1, 4), (2, 5), (3, 6), (4, 3)
(5, 7), (6, 8), (7, 1), (8, 2)
Central Algorithm: # steps = N logN
Fig Illustration of a looping connection setup algorithm

30. Properties of Benes Network
1.) Unique path property of underlying baseline and reverse baseline networks 2.) Binary tree to middle-stage nodes An input can reach 2j-1 nodes at stage j, j <= log2N 3.) Reachability of nodes in baseline/reverse baseline networks: A node in stage i can be reached by 2i inputs and can reach 2n-j+1 outputs 4.) Middles nodes blocked by an existing path

31. Cantor Network . 1 2 N
m = 1
m = log N
Fig Cantor network

32. Cantor Network – Strictly Nonblocking
Cantor Network is SNB : 1.) Let m be # of Benes Network required 2.) Worst case: all other N-1 inputs/outputs busy → there are (N-1) paths to middle nodes 3.) One path meets the binary tree at stage 1 Two paths at stage 2
An example of 8 x8 Benes network
Stage 1
Stage 2 …

33. Cantor Network – Strictly Nonblocking
4.) A node in stage i blocks
5.)

34. 1 2 3 4 5 6 7 8
Connection paths from inputs 1 and 2 intersect with binary tree from the first time in stage 2
If input 4 is connected to this link: a subtree is formed by the three subsequent nodes
Therefore the two lower middle-stage nodes are eliminated from connection by input 3
Fig Binary tree extended from an input to all middle-stage nodes

35. # middle nodes blocked from inputs.

36. Time-Domain SwitchingU X
Space division switch
Fig Performing time-slot interchange using space-division switch

37. Time-Domain Switching
TSI
Write
Read a b c
RAM
Switching in time domain
Write Address Sequence = a, b, c
Read Address Sequence = b, a, c
Fig Direct time slot interchange using random access memory (switching in the time domain)

38. Example for Time-Domain Switching

39. Fig. 2.20. A time-space-time switch
Time-Space-Time Switching
TSI
r x r . n m
n, m : number of time slots per frame at various points
Fig A time-space-time switch

40. Fig. 2.25 A time-space time switch
Time-Space-Time Switching
( i, j ) — data on input i at time-slot j
C(1,3)
B(1,2)
A(1,1)
F(2,3)
E(2,2)
D(2,1)
L(3,3)
H(3,2)
G(3,1)
3 x 3
TSI 1 3 2
Frame
Targeted Outputs
Fig A time-space time switch

41. Time-Space-Time Switching
D(2,1) M U X
TSI
(1)
(2)
(3)
CBA
BAC
EDC
CED
B(1,2)
E(2,2)
C(1,3)
C(1,3)
D(2,1)
A(1,1)
FED
EDF
HAL
LHA
E(2,2)
H(3,2)
F(2,3)
L(3,3)
G(3,1)
G(3,1)
LHG
HGL
BGF
GBF
H(3,2)
B(1,2)
L(3,3)
F(2,3)
Fig Equivalent of time-space-time switching and three-stage space switching

42. 3 x 3 C(1,3) B(1,2) A(1,1) F(2,3) E(2,2) D(2,1) L(3,3) H(3,2) G(3,1)
( i, j ) — data on input i at time slot j
Time Slot 1
Time Slot 2
Time Slot 3
Fig Input-output mapping changes from slot to slot in space-division switch in time-space-time switching

43. These lines correspond to time slot 1 A(1,1)
B(1,2)
F(2,3)
E(2,2)
L(3,3)
H(3,2)
G(3,1)
(1)
(2)
(3)
Module (i) corresponds
to time slot i of
space-division switch in
time-space-time switch
Module (i) corresponds
to input TSI (i) in
time-space-time switch
Module (i) corresponds
to output TSI (i) in
time-space-time switch
Fig Equivalent of time-space-time switching and three-stage space switching
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