1. ECE 721, Spring 2019
Prof. Eric Rotenberg

2. ECE 721, Spring 2019
Prof. Eric Rotenberg

3. ECE 721, Spring 2019
Prof. Eric Rotenberg

4. Canonical Pipeline Stages
Frontend stages
Instructions are physically in-order
Fetch, Decode, Rename, Dispatch
Backend stages
Instructions are physically out-of-order
Schedule, Register Read, Execute, Writeback
Retire
Instructions are processed in-order from Active List
ECE 721, Spring 2019
Prof. Eric Rotenberg

5. Sub-pipelining
Each canonical pipeline stage may be sub-pipelined deeper
ECE 721, Spring 2019
Prof. Eric Rotenberg

6. Challenges for Wide Superscalar
Fetch width limiters:
Taken branches
Multiple branch prediction
Dependencies within rename bundle
Large, highly-ported structures:
Ports scale linearly with superscalar width
Sizes scale superlinearly with width, to expose sufficient ILP
IQ, LQ, and SQ are also associative structures with other specialized logic (e.g., select logic)
Bypass complexity
ECE 721, Spring 2019
Prof. Eric Rotenberg

7. Challenges for Latency-Tolerant Superscalar
Very large PRF and Active List (ROB) needed for memory latency tolerance.
Example:
4-wide superscalar
200-cycle miss penalty
PRF / Active List must have ~800 entries to not block on miss in last-level cache.
ECE 721, Spring 2019
Prof. Eric Rotenberg