1. INSTRUCTION SET DESIGN

2. INSTRUCTION FORMATS ZERO-ADDRESS INSTRUCTION ONE-ADDRESS INSTRUCTION
TWO-ADDRESS INSTRUCTION
THREE-ADDRESS INSTRUCTION

3. DESIGN CRITERIA INSTRUCTION LENGTH
MEMORY/BANDWIDTH REQUIREMENTS
DECODING REQUIREMENTS
TARGET ARCHITECTURE/INTER-OPERATABILITY REQUIREMENTS
BIG ENDIAN/LITTLE ENDIAN FORMAT
REGISTER/STACK-BASED DESIGN

4. ADDRESSING MODES IMMEDIATE ADDRESSING DIRECT ADDRESSING
REGISTER ADDRESSING
REGISTER INDIRECT ADDRESSING
INDEXED ADDRESSING
BASED-INDEXED ADDRESSING
STACK ADDRESSING

5. IMMEDIATE ADDRESSING
THE ADDRESS PART OF THE INSTRUCTION CONTAINS THE OPERAND ITSELF RATHER THAN AN ADDRESS OR OTHER INFORMATION DESCRIBING WHERE THE OPERAND IS.
ADVANTAGES: OPERAND IS FETCHED AT SAME TIME AS INSTRUCTION, HENCE AVAILABLE FOR IMMEDIATE USE; NO EXTRA MEMORY REFERENCE REQUIRED.
DISADVANTAGES: ONLY A CONSTANT CAN BE SUPPLIED THIS WAY. THE NUMBER OF VALUES IS LIMITED BY SIZE OF FIELD.

6. DIRECT ADDRESSING FULL MEMORY ADDRESS OF OPERAND IS SPECIFIED.
DISADVANTAGES: MEMORY LOCATION IS FIXED. CAN BE USED TO ACCESS GLOBAL VARIABLES WHOSE ADDRESS IS KNOWN AT COMPILE TIME.

7. REGISTER ADDRESSING MOST COMMONLY USED ADDRESSING MODE
SIMILAR TO DIRECT ADDRESSING; A REGISTER IS SPECIFIED INSTEAD OF A MEMORY LOCATION.
ADVANTAGES: FASTER ACCESS (IN MOST CHIP ARCHITECTURES, THE REGISTERS ARE LOCATED ON THE CPU CHIP) AND SHORTER ADDRESSES.

8. REGISTER-INDIRECT ADDRESSING
ADDRESS OF OPERAND IS CONTAINED IN A REGISTER. THIS TYPE OF ADDRESS IS CALLED POINTER.

9. INDEXED ADDRESSING
MEMORY IS ACCESSED BY GIVING A REGISTER PLUS A CONSTANT OFFSET (INDEX).

10. BASED-INDEXED ADDRESSING
MEMORY ADDRESS IS COMPUTED BY ADDING UP TWO REGISTERS PLUS AN (OPTIONAL) OFFSET. ONE OF THE REGISTERS IS THE BASE AND THE OTHER IS THE INDEX.

11. STACK ADDRESSING PUSH-POP DESIGN
ADVANTAGES: SHORT INSTRUCTION LENGTH, SIMPLER INSTRUCTIONS
DISADVANTAGES: LINEAR IMPLEMENTATION.n INSTRUCTIONS HAVE TO BE “POPPED” TO REACH THE n+1th INSTRUCTION

12. EXCEPTION HANDLING
TRAPS
INTERRUPTS

13. TRAPS
TRAP: AUTOMATIC PROCEDURE CALL INITIATED BY SOME CONDITION (FLOATING-POINT OVERFLOW, FLOATING-POINT UNDERFLOW, INTERGER OVERFLOW, PROTECTION VIOLATION, UNDEFINED OPCODE, STACK OVERFLOW, DIVISION BY ZERO) CAUSED BY THE PROGRAM.
HARDWARE-BASED MECHANISM. FASTER THAN SOFTWARE IMPLEMENTED EXCEPTION HANDLING.

14. TRAPS
WHEN A TRAP OCCURS, THE FLOW OF CONTROL IS SWITCHED TO SOME FIXED MEMORY LOCATION INSTEAD OF CONTINUING IN SEQUENCE. AT THAT FIXED LOCATION IS A BRANCH TO A PROCEDURE CALLED THE TRAP HANDLER, WHICH PERFORMS SOME APPROPRIATE ACTION, SUCH AS PRINTING AN ERROR MESSAGE.

15. INTERRUPTS
INTERRUPTS: CHANGES IN THE FLOW OF CONTROL CAUSED NOT BY THE RUNNING PROGRAM, BUT BY SOMETHING ELSE (EG., I/O)
INTERRUPT STOPS THE RUNNING PROGRAM AND TRANSFERS CONTROL TO AN INTERRUPT HANDLER, WHICH PERFORMS SOME APPROPRIATE ACTION. WHEN FINISHED, THE INTERRUPT HANDLER RETURNS CONTROL TO INTERRUPTED PROGRAM.
ADDITIONAL DETAILS IN SECTION 5.6.5

16. TRAPS VS.INTERRUPTS
TRAPS ARE CAUSED DIRECTLY BY PROGRAM, WHILE INTERRUPTS ARE, AT BEST, CAUSED INDIRECTLY BY THE PROGRAM.
TRAPS ARE SYNCHRONOUS WITH THE PROGRAM WHILE INTERRUPTS ARE ASYNCHRONOUS. IF THE PROGRAM IS RERUN WITH THE SAME INPUT, TRAPS WILL RECOOUR IN THE SAME PLACE EACH TIME, WHILE INTERRUPT-OCCURANCE MAY VARY.