1. FIGURE Read and write bus cycle timing for the 8086 and 8088 microprocessors. Each bus cycle requires four T states.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

2. FIGURE Basic read and write bus cycle timing for the 386, 486, and Pentium processors. Each bus cycle requires two T states.
John Uffenbeck The 80x86 Family: Design, Programming, and Interfacing, 3e
Copyright ©2002 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

3. Memory access time provided by Different processors

4. taccess-processor > taccess-memory
MEMORY CHIPS ARE RATED BY THEIR ACCESS TIMES.
definition: Memory Access time isthe time from receiving the address to deliver the data.
taccess-processor > taccess-memory
Otherwise wait states should be added.
taccess-processor and taccess-memory are given by the manufacturer in the data sheet.
taccess-processor is clock dependent (1.5T for 8086 an 2.3T for others)
Accesses time diff tdif= taccess-memory - taccess-processor
# of wait states = tdif / T (greatest integer)

5. Burst Cycle 16 bytes in 486 in 2-1-1-1 Read only.
32 bytes in Pentium Read and write.
32 bytes in Pentium using address pipelining.

6. Data Transfer Rate Let us call:
Maximum number of bytes that can be transferred in one BUS CYCLE
Duration (time) for one BUS CYCLE
Let us call:
“Maximum number of bytes that can be transferred in one BUS CYCLE” : Bytes
One BUS CYCLE duration=nT=n/f
Where n= the number of clock cycles per bus cycles
f is the bus clock frequency
Data transfer rate =
Bytes  f n

7. Performance Gap DRAM microprocessor 1980 1984 1986 1988 1990 1992 1994
1996
1998
2000
1982