1. Embedded Development Tools
System Trace
Embedded Development Tools

2. What is Trace?
Advanced debugging capability that allows capturing code execution and system events in real-time
Extension to the basic JTAG debug capabilities of the TI processors
Useful to detect complex, intermittent bugs and profile and fine tune code performance
Two types of trace:
Processor trace: Inspects the code execution
Performs real-time gathering of instructions being executed in a processor
System trace (STM): Oversees system behaviour
Set of built-in capabilities on the device that monitors synchronization and timing between cores and on-chip peripherals

3. Why Do I Need Trace?
Useful to detect complex, intermittent bugs and profile and fine tune code performance
If you are stuck with an intermittent or complex problem in the code, Processor Trace is usually your last line of defense to see the execution history
If you happen to have runtime problems but can’t identify what is causing the missed real-time deadlines, both Processor and System Trace help evidence it
If the system does not meet the expected or calculated power requirements, System Trace helps
Multiple uses and scenarios can have Trace as a helping hand to debug problems in the system
For example, the ability of Core Trace to “see” the entire past execution history allows finding places where the code behaves erratically or took an unexpected branch.
Also, if the system is running slow or is returning incorrect or corrupt data, it is possible to use a combination of Core and System Trace to track what can be happening.
In certain devices it is also possible to evaluate if cores are actually powered down and not hung waiting for interrupts or other events.

4. What is System Trace?
Capture several system events that happen inside the device
Attach timestamps to each event
Send data back to Code Composer Studio for post processing analysis using the advanced visualization tools
External memory (EMIF) throughput
Power domain status
The buffer can be either inside the device (ETB) or outside the device via dedicated pins (Pin Trace) to an external Trace pod (XDS560v2 STM)
ETB: Smaller data set (Buffer size: 2 – 8 KB)
XDS560v2 STM: Larger data set (Buffer size:128 MB)
Expanding on the concept of System Trace, think of it as a type of trace that monitors the entire device and not only the core processor. In other words, it monitors the core processor status, internal buses on the device and peripherals via special modules called CP tracers. Therefore this trace does not capture instructions but event messages (memory accesses, power status, etc.) and, similarly to Core Trace, it sends them to the host PC together with timestamps for further analysis.
Once this data is transferred to the host PC and processed by CCS, the event messages are correlated with the source code and the advanced visualization tools can be used to see how the code interacts with the system.
Just for comparison with Core Trace, system trace messages do not occur with the same frequency as instructions, therefore its implementation is much less complex, although they still require some hardware buffering. That is the reason why system trace is not available in all devices and, similarly as for Core Trace, for the ones who have this feature there are two implementations with different levels of complexity: Embedded Trace Buffer, or ETB, and STM pin trace using an external emulator pod.
[Alternative text]
Expanding on the concept of System Trace, the idea behind it is to monitor how the multiple components of a device interact in real-time. These components are single or multiple cores, peripherals, bus controllers, memory, etc. Therefore this trace does not capture instructions but event messages (memory accesses, power status, etc.) and, similarly to Core Trace, it stores them on the host PC together with timestamps for further analysis.

5. What Is System Trace?
Trace capability that monitors synchronization and timing between cores and on-chip peripherals
Ability to track bus and peripheral activity and monitor data throughput
Trace data combined synchronously with output from the other cores in the system to give you a picture of the order of events on separate CPUs
Provides system level visibility to software thread execution and hardware performance

6. What Can I Do With It? Hardware-accelerated "printf" ability
STM Library (STMLib) provides printf, message logging and data dump APIs for use to instrument your application
Configure Common Platform Tracer (CP_Tracer or CPT) on supported devices to monitor activity on the associated bus and export data via STM
CPT data is exported as STM messages that can be collected with the ETB or XDS560v2 STM
CPT can be programmed through CPTLib or with CCS/AET (via Breakpoints view)
Debug multi-core environments
STM messages from each core are identified and globally time stamped by hardware
Provides a global, time-correlated view of software execution across cores
See both software thread execution and hardware performance correlated in time
See the synchronization and timing between cores and on-chip peripherals in their application as well as the performance of cores and key device interfaces

7. Types of System Trace Device Any XDS emulator XDS560v2 STM Trace ETB
Peripherals
EMIF
USB or Ethernet
CP Tracer
CP Tracer
Memory
CP Tracer
14, 20 or 60-pin
JTAG Connector
XDS560v2 STM Trace
Processor Subsystem
Core
As shown in the previous slide, system trace can be done either via the ETB or using external pins and a XDS560v2 STM.
All the different system components of a device communicate to the STM Module via the CP Tracer modules, which either stores the information in the internal ETB buffer or sends it to the external pins to be stored in the STM Buffer of the XDS560v2 STM
Similarly to Core Trace, the same benefits and disadvantages between the two technologies are applicable. ETB is able to capture a smaller sample of system messages, and it only operates in circular mode, which means that old messages are overriden by newer ones. No hardware changes are necessary and it allows performing STM trace with any XDS emulator.
On the other hand, the STM Buffer can have any size and allows additional configurability such as operation in both circular and one-shot mode, therefore allowing to retrieve the exact history of system messages up to a given point of interest. The additional hardware usually does not involve a major redesign and can be optional in several cases, although some devices do not support STM with the common 14-pin JTAG connector.
At last, the fact the trace buffer is outside the device requires the use of an emulator equipped with a STM Buffer and Decoder, and two models can be chosen: a XDS560v2 STM or a XDS PRO Trace.
CP Tracer
USB or Ethernet
20 or 60-pin JTAG Connector
ETB
STM Buffer
Datapaths:
- ETB Trace
- STM Pin Trace
STM module

8. Types of System Trace – ETB Trace
Device
Any XDS emulator
Peripherals, EMIF
PC with CCS
CP Tracer
Statistics collection
Processor Subsystem 1
CP Tracer System Message units
USB or
Ethernet
Core
14, 20 or 60-pin JTAG Connector
STM module
Processor Subsystem 2
BUS watchpoint and traffic monitors
CP Tracer System Message units
Core
Key features:
Buffer size is limited (typically 2k to 8k)
It only features circular mode
No modifications to the hardware are needed
Any XDS emulator can be used
ETB
As shown in the previous slide, system trace can be captured using the Embedded Trace Buffer or ETB. This is the same buffer used for Core Trace, with the difference that the information that fills this buffer is re-routed from the STM module then read by the external JTAG emulator.
Similarly to Core Trace, the same benefits and disadvantages of ETB Trace are applicable. ETB is able to capture a smaller sample of system messages, and it only operates in circular mode, which means that old messages are overriden by newer ones. No hardware changes are necessary and it allows performing STM trace with any XDS emulator and any JTAG connector.

9. Types of System Trace – Pin Trace
Device
XDS560v2 STM Trace
Peripherals, EMIF
PC with CCS
CP Tracer
Statistics collection
Processor Subsystem 1
CP Tracer System Message units
USB or
Ethernet
Core
STM Buffer
STM module
20 or 60-pin JTAG Connector
Processor Subsystem 2
BUS watchpoint and traffic monitors
CP Tracer System Message units
Core
Key features:
Buffer size is virtually unlimited (up to 64MB)
It features circular and one-shot modes
Modifications to the hardware are needed, but minimal
Both XDS560v2 STM and XDS560v2 PRO Trace emulators can be used
On the other hand, when using STM Pin Trace the STM Buffer is external to the device and the data is exported through extra JTAG pins.
Similarly to Core Trace, STM Pin Trace has the same advantages and disadvantages of pin trace are applicable. The STM Buffer can be very large and allows additional configurability such as operation in both circular and one-shot mode, therefore allowing to retrieve the exact history of system messages up to a given point of interest. The additional hardware usually does not involve a major redesign and can be optional in several cases, although some devices do not support STM with the common 14-pin JTAG connector.
At last, the fact the trace buffer is outside the device requires the use of an emulator equipped with a STM Buffer and Decoder, and two models can be chosen: a XDS560v2 STM or a XDS PRO Trace.

10. STM SW Messages Overview
Sort by core, type of message (driver, OS, thread), etc.
See sequence of operation across cores.

11. Processor Trace vs. System Trace
Processor (Core)
Requirements:
XDS560v2 Pro Trace w/60-pin header
ETB
Single CPU visibility
Features:
Capture activity on Program and Data bus for that CPU
Trace the complete program address execution
Trace all of the data writes to a specific location or range of locations
System (STM)
Requirements:
XDS560v2 STM w/60-pin header
ETB
System level visibility
Multi-core debug
Features:
Hardware-accelerated, multi-core "printf" ability
CPTracer monitoring
Trace data combined synchronously with the output from the other cores in the system to give you a picture of the order of events on separate CPUs

12. STM SW Messages (Core 0) Trace Display lists all the messages
Logic Analyzer displays a timeline for each function

13. CP Tracer STM Data – CorePac0 access to CorePac1 L2 Data
Red - MB/s of CorePac0 accesses to CorePac1 L2 memory
Purple - Total Transactions for all masters accessing CorePac1 L2
Green - Average Access width in bytes
Turquoise - % of CorePac1 L2 bandwidth used by CorePac0
Pink - Overall Average latency