1. Implementation Of Full Adder Using Spartan-3E FPGA
(STB99061)
NATIONAL INSTITUTE OF TECHNOLOGY,
TIRUCHIRAPPALLI –
3-DAY TUTORIAL ON VERILOG HDL
Organized by
IEEE STUDENT BRANCH NIT TRICHY
Implementation Of Full Adder Using Spartan-3E FPGA
Ms. Vinitha Bobbili
M.Tech Scholar NIT-T
Department of Electronics and Communication Engineering
17 September 2019

2. FPGA Design Flow:

3. Full Addeer:
module adder(s,cy,a,b,c_in ); input a,b,c_in; output s,cy; assign s=a^b^c_in; assign cy=(a^b)&c_in|(a&b); endmodule

4. Spartan-3E Starter Kit:

5. bit file generation :
Verilog code-> Synthesis -> ucf >implement design(translate,map,place&route) ->generate programming file.

7. FPGA Configuration: Impact Tool

8. a =b=c=0, s=cy=0 a=b=0 c=1 s=1 cy=0
Output :
a =b=c=0, s=cy= a=b=0 c=1 s=1 cy=0

9. a=b=1 c=0 s=0 cy=1 a=b=c=1 s=cy=1

10. Thank you