1. Sizing Structures Fixed relations Empirical (simulation-based)
Relation of free list size to phys. reg. file size
Relation of phys. reg. file size to active list size
RMT and AMT
Empirical (simulation-based)
Active list, issue queue, shadow maps
ECE 721, Spring 2019
Prof. Eric Rotenberg

2. 1. Free List Size w.r.t. Phys. Reg. File Size
Committed registers can’t be free
Suppose all speculative registers are free (i.e., pipeline empty)
free list size = phys. reg. file size – # logical registers
Free List
Physical Register File
# speculative registers
# committed registers
# logical registers in ISA
ECE 721, Spring 2019
Prof. Eric Rotenberg

3. 2. Phys. Reg. File Size w.r.t. Active List Size
# physical registers = # committed registers + # speculative registers
# committed registers = # logical registers
# speculative registers
What if each active (speculative) instruction has a destination register?
Upper bound: # speculative registers = active list size
# physical registers = # logical registers + # entries in active list
Could have fewer than this, because some instructions (stores, most branches) don’t have a destination register
ECE 721, Spring 2019
Prof. Eric Rotenberg

4. 3. RMT and AMT Only one rename map table Only one arch. map table
Map table dimensions
# entries = # logical registers
# bits per entry = # bits in a physical register tag = log2(# physical registers)
ECE 721, Spring 2019
Prof. Eric Rotenberg

5. 4. Window size
Active list is overall window into dynamic instruction stream
Issue queue is dynamic scheduling window
# shadow maps depends on number of unresolved branches in issue queue
These must be empirically determined because they depend on nature of ILP in programs and target fetch/issue width of processor (N)
Greater N requires larger inspection scope for finding more independent instructions that can issue in parallel
Inspection scope also depends on data dependencies, interleaving of dependent/independent instructions, and latencies (cache misses, etc.)
ECE 721, Spring 2019
Prof. Eric Rotenberg

6. Window sizing Short answer
All resources must be large enough to not stall fetch stage
Implies IPC = N instr./cycle for N-way superscalar
ECE 721, Spring 2019
Prof. Eric Rotenberg

7. Sizing Structures (cont.)
data dependencies, cache misses, etc.
in typical programs N
Issue Queue(s) / Active List
Physical Register
File
Shadow Maps
Free List
ECE 721, Spring 2019
Prof. Eric Rotenberg

8. “Queuing Theory” Perspective
Little’s Law:
# customers = arrival rate • service time
4 instr./cycle
4 instr./cycle
Issue Queue
Issue Queue
4 instr./cycle
4 instr./cycle
Avg. wait time of an instruction = 5 cycles
Avg. wait time of an instruction = 8 cycles
IQ size ~ (5 cycles x 4 instr./cycle) = 20 instr.
IQ size ~ (8 cycles x 4 instr./cycle) = 32 instr.
ECE 721, Spring 2019
Prof. Eric Rotenberg

9. Size of Issue Queue (IQ)
Little’s Law
# customers = arrival rate x service time
IQ size = (N) x (average wait time)
Average wait time depends on data dependencies, cache misses, etc.
Bottom line
Use simulation to find minimum IQ size that maximizes IPC
ECE 721, Spring 2019
Prof. Eric Rotenberg

10. Size of Active List (Reorder Buffer)
Like issue queue except longer wait time
Instruction enters issue queue and active list at dispatch
Instruction leaves:
Issue queue when it issues (OOO)
Active list when it retires (in-order)
 stays longer in active list
Little’s Law: Active list size > issue queue size
How much larger? Run simulations.
ECE 721, Spring 2019
Prof. Eric Rotenberg

11. # Shadow Maps # shadow maps
A shadow map is allocated to each unresolved branch
Map is reclaimed when branch resolves
# shadow maps = average # unresolved branches in processor
How many? Run simulations.
ECE 721, Spring 2019
Prof. Eric Rotenberg