1. Verify chip performance
History: The ASD in Agilent 500 nm technology (J. Oliver, C. Posch, E. Hazen)
development of the chip (8-channels)
production of 50k packaged chips  test of threshold spread among the channels/ASD leads to 3 categories
of quality (< 12, <16, <20 mV)  rad-tol tests up to 1 Mrad: no failures  the lvds-driver allows for undefined logic levels  hangups in the TDC !
 reliable operation in „edge mode“
 very low failure rate of ASDs
Outputs with undefined logic (“half-pulses”)
Programmed dead time not respected by noise pulses
50 New ASDs needed for the Phase-II Upgrade of the Muon Spectrometer
The Agilent technology is no more available. Go to new design in IBM 130 nm, supported by CERN
Design aims:
 match the “good” properties of the
Agilent chip
 fix the lvds driver problem to be able to use “pair mode”, allowing a factor of 2 higher hit rates at the HL-LHC
New ASD in IBM 130 nm technology
prototype of the analog part of a 4-chan. vs  good matching of shape and gain (1,5%)  peaking time ~ 25ns instead of ~15 ns
new version, incl. digital part (4 channels)  peaking time still > 15 ns
 functional problems with Wilkinson AD
cooperation MPI and Univ. Milano  modif. to reduce parasitic capacitances  redesign of Wilkinson and lvds driver  pre-tapeout tests: SPICE, PLX, LVS, PVT
2014 submission of new chip in november
2015 chips returned in febr. 2015, tests in april-september (still ongoing)
Verify chip performance
First use SPICE simulation, then, after layout, Post Layout eXtracted simulation (PLX) to check on the following parameters:
Peaking time vs. Input charge
Peak output Voltage vs. Input charge
Frequency response
Transient noise
Wilkingson discharge time vs. Input charge
DISCR delay
Serial interface and DACs
… more …
Pre-amp, DA1, DA2, DA3
For all parameters: check dependence on Process, Voltage and Temperature (PVT)
 worst case (Corner) simulation
E.g.: PLX vs. SPICE simul. of peak time
First results testing the ASD vs. 4
Threshold Scan of the ASD vs. 4
50 ns/div
Peaking time ~12 ns
100 mV
200 mV
0 mV
-1.2 V
-0.8 V
-0.4 V
-1.6 V
-2.0 V
Analog test output looks OK:
peaking time: ~ 12 ns
ADC mode looks OK: output varies with pulse height
Output freq. for 7 chan‘s of a chip vs. threshold
10 kHz
Input:
d-pulse of 20 fC at 10 kHz
5 kHz
(50% eff.)
8 mV thresh. variat. among 7 chan‘s
NB: ch. #7 (with analog output!) is off-scale by 30 mV
New and old Chip Layout
~2,2 mm
3 mm
130 nm IBM: 6.6 mm2
3.2 mm
2.2 mm
500 nm Agilent: 11.8 mm2
0.38 mm
0.4 mm
1.4 mm
Range of linearity up to ~ 90 fCb
Improvements for next submission:
remove coupling from Discr. to Input
improve ADC uniformity (pulse length vs. charge)
improve dead-time uniformity
fix some errors in the JTAG coding
add test pulse function
go for next submission in nov/dec