1. ESSCIRC/ESSDERC 2019, Cracow, Poland
ESSCIRC/ESSDERC 2019 Presentation (A Template) Name and Surname Department Name Institution Name, Country September 23-26, 2019
ESSCIRC/ESSDERC 2019, Cracow, Poland

2. ESSCIRC/ESSDERC 2019, Cracow, Poland
Outline
Text and Figures Template
Font sizes, bullets, sub-bullets
drawing line thicknesses, waveforms and graphs
Use of figures, colors
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

3. Slide Title Uses 32-Point Verdana
14 mil
Trace
0.7 mil
FR4 substrate
(er = 4.5)
7 mil
Ground plane
1.4 mil
Keep figures on top of slides; bullets underneath
For main bullets, use 20-point Verdana: 24-point better
For sub-bullets, use 18-point Verdana: 20-point better
Do not use too many sub-bullets
Try your best to limit each bullet to one line
If a bullet becomes longer, break it into two bullets
If you are not planning to cover a bullet, do not include it
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

4. ESSCIRC/ESSDERC 2019, Cracow, Poland
Figure Labels and Text
I(z,t)
I(z,t)
I(z+Dz,t)
RDz
LDz
V(z,t)
V(z,t)
GDz
CDz
V(z+Dz,t) z
Z = R+jwL
, Y = G+jwC
Z0 = (Z/Y)½
g = (ZY)½
Use Verdana for figure labels and figure text
Keep the minimum font size in figures to 18
If needs be, make some labels in figures bold
Try to include a figure at least on every other slide
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

5. ESSCIRC/ESSDERC 2019, Cracow, Poland
Drawing Lines
D Q CK
PRBS
Y28
Y31
Use a minimum thickness of “2 ¼” in power point
A thinner line may not show up on screen
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

6. Use of Solder Dots Use solder dots to avoid connection ambiguity VRN
VRP
VB2 IN
OUT
1st stage transconductance
2nd stage
transimpedance
VB1
Use solder dots to avoid connection ambiguity
* Y. Tomita et al., JSSC, Apr. 2005, pp
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

7. ESSCIRC/ESSDERC 2019, Cracow, Poland
Waveforms and Graphs
(VRP=0V)
(VRN=0.8V) 20
VRP=0.45V
VRN =1V 20
0.4V
0.3V
0.9V
40dB/dec
0.2V 0V
0.8V
Gain [dB]
Gain [dB] 10
0.75V
20dB/dec
0.7V
-20
0.01
0.1 1 10
0.1 1 10
GHz
GHz
Results should be readable (min. font size 18)
Do NOT simply import from Cadence viewing tool
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

8. ESSCIRC/ESSDERC 2019, Cracow, Poland
Use of Colors: Use RGB
s(t)
Time CK IN
OUT
PMOS switch
Strong-ARM latch
Bias
CML latch
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

9. ESSCIRC/ESSDERC 2019, Cracow, Poland
Equations
fVCO fe
fOUT
fin
Kpd
HLPF(s)
KVCO/s
Jitter Transfer
Jitter Generation
Use font size similar to those in figures
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

10. ESSCIRC/ESSDERC 2019, Cracow, Poland
More on Using Colors
fVCO fe
fOUT
fin
Kpd
HLPF(s)
KVCO/s
Jitter Transfer
Jitter Generation
fOUT / fin
fOUT / fVCO dB
Jitter Freq.
fcorner
Use colors as necessary, but not more
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

11. ESSCIRC/ESSDERC 2019, Cracow, Poland
Papers to See This Year
Suggest papers based on Advance Program
11.3, 11.4: good example on burst-mode CDR
Session 5 Relevant Papers:
5.1: 8Gb/s 5-FFE, analog EQ, 2-DFE, eye-tracking CDR
5.2: 40Gb/s adaptive EQ and CDR
Session 25 Relevant Paper:
25.9: 8x3.2Gb/s link with collaborative timing recovery
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland

12. Include Key References
Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw Hill, 2003.
R. C. Walker, “Designing Bang-Bang PLL’s for Clock and Data Recovery in Serial Data Transmission Systems,” B. Razavi, Ed: IEEE Press, 2003, pp
L. DeVito et al., “A 52MHz and 155MHz clock-recovery PLL,”, ISSCC 1991, paper 8.6
Y.M.Greshishchev et al., “A Fully Integrated SiGe Receiver IC for 10Gb/s Data Rate”, ISSCC2000, paper 3.2. Expanded version in JSSC, Dec. 2000, pp
J. Lee et al., “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” JSSC, Sep. 2004, pp
H. Takauchi et al., “A CMOS Multichannel 10-Gb/s Transceiver,” ISSCC 2003, paper 4.2. Expanded version in JSSC, Dec. 2003, pp
N. Nedovic et al., “A 40-to-44Gb/s 3x Oversampling CDR 1:16/DEMUX,” ISSCC 2007, paper Expanded version in JSSC, Dec. 2007, pp
M. van Ierssel et al., “A 3.2Gb/s Semi-Blind-Oversampling CDR”, ISSCC 2006, paper Expanded version in JSSC, Oct. 2007, pp
T. H. Lee et al., “A 155-MHz Clock Recover- and Phase-Locked Loop,” JSSC, Dec. 1992, pp
J. McNeill, “Jitter in Ring Oscillators,” JSSC, June 1997, pp
Name Surname
ESSCIRC/ESSDERC 2019, Cracow, Poland