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ECE 721 Modern Superscalar Microarchitecture

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Presentation on theme: "ECE 721 Modern Superscalar Microarchitecture"— Presentation transcript:

1 ECE 721 Modern Superscalar Microarchitecture
Spring 2019 Prof. Eric Rotenberg ECE 721, Spring 2019 Prof. Eric Rotenberg

2 Logical Registers Logical registers Ex: Alpha Architecture
Program registers Ex: Alpha Architecture 32 logical integer registers (r0-r31) 32 logical floating-point registers Also called architectural registers ECE 721, Spring 2019 Prof. Eric Rotenberg

3 Physical Registers Physical registers
Hardware registers Ex: Alpha Microarchitecture 80 physical integer registers (p0-p79) 72 physical floating-point registers ECE 721, Spring 2019 Prof. Eric Rotenberg

4 Renaming Renaming Assign a unique physical register to a logical register Number of physical registers > number of logical registers Multiple definitions of a logical register are each assigned a unique physical register ECE 721, Spring 2019 Prof. Eric Rotenberg

5 Structures (required)
Physical register file Rename map table Free list List of unused registers in physical register file Active list Active instruction: Instruction that has been dispatched but not yet retired Active list: List of all active instructions in program order Equivalent to the Reorder Buffer (ROB) ECE 721, Spring 2019 Prof. Eric Rotenberg

6 Structures (optional)
Architectural map table Recovery from exceptions and mispredictions (branch, load, etc.) Restore rename map table to committed state Shadow map tables Recovery from branch mispredictions Restore rename map table to what it was just after the branch ECE 721, Spring 2019 Prof. Eric Rotenberg

7 Side notes Alternate names for map tables Optional structures
Rename map table: frontend map table Architectural map table: backend map table Optional structures Architectural map table is optional Shadow map tables are optional Whether or not these exist depends on recovery strategy. Active list alone can be used for recovery. Recovery strategies affect contents of active list and existence of the architectural and shadow map tables. More on this later… ECE 721, Spring 2019 Prof. Eric Rotenberg

8 Renaming Rename logical source registers
Obtain mappings from rename map table Rename logical destination register Pop a free physical register from the free list Assign the physical register to the logical destination register Update rename map table to reflect the new mapping ECE 721, Spring 2019 Prof. Eric Rotenberg

9 Renaming Example load r1, 16(r2) add r3, r1, #1 load r1, 20(r2)
sub r4, r1, #1 add r3, r1, #1 ECE 721, Spring 2019 Prof. Eric Rotenberg

10 Renaming Example load r1, 16(r2) load p67, 16(p11)
Rename Map Table (before) Rename Map Table (after) load r1, 16(r2) r0 p10 r1 p8 r2 p11 r3 p33 r4 p46 … r31 p2 r0 p10 r1 p67 r2 p11 r3 p33 r4 p46 … r31 p2 p11 head tail head tail load p67, 16(p11) p67 p19 p27 p28 … p5 p67 p19 p27 p28 … p5 Free List (before) Free List (after) p67 ECE 721, Spring 2019 Prof. Eric Rotenberg

11 Renaming Example add r3, r1, #1 add p19, p67, #1
Rename Map Table (before) Rename Map Table (after) add r3, r1, #1 r0 p10 r1 p67 r2 p11 r3 p33 r4 p46 … r31 p2 r0 p10 r1 p67 r2 p11 r3 p19 r4 p46 … r31 p2 p67 head tail head tail add p19, p67, #1 p67 p19 p27 p28 … p5 p67 p19 p27 p28 … p5 Free List (before) Free List (after) p19 ECE 721, Spring 2019 Prof. Eric Rotenberg

12 Renaming Example load r1, 20(r2) load p27, 20(p11)
Rename Map Table (before) Rename Map Table (after) load r1, 20(r2) r0 p10 r1 p67 r2 p11 r3 p19 r4 p46 … r31 p2 r0 p10 r1 p27 r2 p11 r3 p19 r4 p46 … r31 p2 p11 head tail head tail load p27, 20(p11) p67 p19 p27 p28 … p5 p67 p19 p27 p28 … p5 Free List (before) Free List (after) p27 ECE 721, Spring 2019 Prof. Eric Rotenberg

13 Renaming Example sub r4, r1, #1 sub p28, p27, #1
Rename Map Table (before) Rename Map Table (after) sub r4, r1, #1 r0 p10 r1 p27 r2 p11 r3 p19 r4 p46 … r31 p2 r0 p10 r1 p27 r2 p11 r3 p19 r4 p28 … r31 p2 p27 head tail head tail sub p28, p27, #1 p67 p19 p27 p28 … p5 p67 p19 p27 p28 … p5 Free List (before) Free List (after) p28 ECE 721, Spring 2019 Prof. Eric Rotenberg

14 Renaming Example load r1, 16(r2) load r1, 20(r2) sub r4, r1, #1
add r3, r1, #1 load p67, 16(p11) add p19, p67, #1 load p27, 20(p11) sub p28, p27, #1 load p67, 16(p11) load p27, 20(p11) add p19, p67, #1 sub p28, p27, #1 ECE 721, Spring 2019 Prof. Eric Rotenberg

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