1. Microprocessor
Lecture 7 (8086 Registers)

2. Microprocessor 8086
8bit microprocessor, 16bit microprocessor 32bit microprocessor, What does No. of bits microprocessor mean?
It’s mean, for example 16bits microprocessor:
all internal and external registers are 16 bits width, and
16 bits data bus to transfer data in and out of the CPU
The 8086 has a 16 bit data bus and a 20-bit address bus that can address 2^20, that is 1 MB of unique memory.

3. Microprocessors Difference
Instruction Set: operations, addressing modes
Registers: size, number
Address bus : size (number of bits)
Data bus: size
Control bus: functions
clock speeds

4. Simple CPU

5. Microprocessor Architecture
Composition of CPU
Control Unit
Generates control/timing signals
Controls decoding/execution of instructions
ALU
Used during execution of instructions
Mathematical operations: * / + - etc.
Logical operations: shift, rotate
Registers
Instruction Pointer Counter: Holds address of instruction being executed
Instruction Register: Holds instruction while it's decoded/executed
Stack Pointer: Address of top of stack
Accumulator: Result of ALU operations
General-Purpose Registers : Hold temporary results or addresses during execution of instructions Write results to memory

6. Microprocessor Architecture
Instruction Execution
Performs Fetch/Decode/Execute cycle
Fetch instruction from primary memory
Increment Program Counter
Decode
Fetch operands from memory
Execute instruction
Write results to memory
Fetch Time depends on
Access time of primary memory
Activity on System Bus
Decode/Execute Time taken depends on
System Clock speed (frequency)
Type of instruction

8. Microprocessor 8086 architecture
Intel implemented the concept of pipelining in 8088/86 by splitting the internal structure of microprocessor into two sections:
Execution Unit EU: executes instructions previously fetched
Bus Interface Unit BIU: access memory and peripherals
The two sections work simultaneously
The EU has no connection to the system buses. It receives and outputs all of its data through the BIU. The execution unit, or EU, handles the arithmetic and logical operations on the data and has a 6-byte first-in, first-out (FIFO) Instruction queue
The main linkage between the two functional blocks is the instruction queue, with the BIU looking ahead of the current instruction being executed in order to keep the queue filled with instructions for the EU to decode and operate on.

9. Pipelining
In the 8085 microprocessor, fetch the instruction form the memory, then execute it. And then fetch again and execute it, and so on.
Pipelining is allow the CPU to fetch and execute at the same time.

10. Registers of 8086 General register used as.
Register Name
bits
Category
AX, BX,CX,DX 16
General
AH,AL, BH,BL, CH,CL, DH,DL, 8
SP(stack pointer),BP(base pointer)
Pointer
SI(source index),DI(destination index)
Index
CS(code segment),DS(data segment),SS(stack segment),ES(extra segment)
Segment
IP(instruction pointer)
Instruction
FR(flag register)
Flag
General register used as.
AX accumulator, BX base addressing ,CX counter in loop operations, and Dx point to data in I/O operations

11. Microprocessor 8086 architecture
Registers: are used to information temporarily .the information can be one or two bytes of data, or the address of data.
General purpose registers in 8086 MP can be accessed as either 16bit or 8 bit registers
All other registers can be accessed only
as the full 16 bits
Pointers and Index Registers These registers are used as memory pointers
MOV AH,[SI]
SI is thus inter-preted as "pointing" to the
desired memory location
AH will store 26H

12. Microprocessor 8086 architecture
The Fetch and Execute Cycle
The organization of the processor into a separate BIU and EU allows the fetch and execute cycles to overlap.
The BIU outputs the contents of the instruction pointer register (IP) onto the address bus.
Register IP is incremented by one to prepare for the next instruction fetch.
Once inside the BIU, the instruction is passed to the queue: a first-in/first-out storage register.
Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution.
While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.
Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.
During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.
The cycle continues, with the BIU filling the queue with instructions and the EU fetching and executing these instructions.