1. Lab 0: Groups and Equipment
Course: ENGG*2410
Start date: Week #1 (Sep 11th – Sep 15th)

2. Agenda
Intro to labs
Reports
Academic Misconduct
Groups and Equipment

3. Intro to Labs Nine labs (not including lab 0)
Lab 1: Introduction to TTL Logic Design
Lab 2: Design Entry using Schematic Capture
Lab 3: Design Entry using VHDL
Lab 4: Advanced Combinational Logic
Lab 5: Arithmetic Circuits using VHDL
Lab 6: Sequential Logic Design (Flip Flops)
Lab 7: Sequential Logic Design (Seq. Recognizer)
Lab 8: Datapath Design
Lab 9: Control (Algorithmic State Machines)

4. Intro to Labs Check Lab manual for the due dates
All labs are 1 week long
Labs are demonstrated to the TA’s during the lab time
Reports are due in the next lab time.
Deposit reports in dropbox.
9 Labs are 20% of your mark, but not necessarily 2.5% each

5. Intro to Labs TTL Logic will be used in the first lab only
NEXYS 3 (Spartan 6) Evaluation board combined with ISE will be used starting from lab 2
You will get all your equipment from Phil Watson today for all the labs
Feel free to ask for other equipment as required (ex resistors etc).

6. Intro to Labs NO food or drink in the labs
Please clean up after yourselves
No one is scheduled to be in the labs on the weekends
Watch out for that big red button
Ensure your equipment is functional before the weekend before the due date

7. Reports 5 standard sections: Problem statement
Assumptions and Constraints
System Analysis, Design and Justifications of Decisions
Hardware
Result Analysis

8. Report Problem Statement Assumptions and Constraints
State briefly what you are doing in the lab, what the goals of the lab are
Assumptions and Constraints
Any assumptions/constraints you have made
Don’t just restate the problem statement

9. Report System Overview and Justification
Give a brief description of how the system works and why it was designed like that
Give us enough information so that we know how your system works

10. Report Hardware Used components and their specifications Schematic
Brief explanation of operation
Any required calculations
Timing diagram if appropriate (i.e Simulation)

11. Report Result Analysis
How you would improve upon your Lab given more time.
Problems encountered during the lab.
Your approach to debugging the problem.

12. Evaluation Criteria The lab mark will be out of 20.
2 marks for the lab preparation
8 marks for the demonstration
10 marks for the report

13. Academic Misconduct
Reports and demos are submitted as a group, but it is a SINGLE group effort
You may talk with other groups but sharing codes or reports is NOT ALLOWED
Copying reports from previous years is also NOT ALLOWED
If we find copying we are REQUIRED to report it

14. Groups and Equipment Every 3 students per Group.
Pick up your equipment from Phil Watson.
Before you leave, check your equipment:
Wires, Resistors, LED, and TTL logic chips.
Logic Probes.
Bread Board.
NEXYS 3 (Spartan 6) Board.