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Magic-State Functional Units
Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures OCT 24, 2018 Ding, Y., Holmes, A., Javadi-Abhari, A., Franklin, D., Martonosi, M., & Chong, F. T. ArXiv: DOI: /MICRO
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Background Our Techniques Results OUTLINE 1
Magic-State Distillation and Braiding 2 Our Techniques Concatenation and Force-directed Annealing 3 Results
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Operations on Error-Corrected Quantum Computers
FAULT-TOLERANT QC Operations on Error-Corrected Quantum Computers Easy single-qubit gates: Difficult 2-qubit gate: CNOT gate H X Z Expensive to implement: requires braiding Difficult single-qubit gate: T gate |𝜓⟩ T T|𝜓⟩ |𝑇⟩ Useful applications contain a significant number of T gates. Consume: 1 magic state Expensive to implement: requires magic state distillation
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MAGIC-STATE DISTILLATION
Magic State Distillation is Expensive Quantum Chemistry *Ising Model of spin chain with size 500. Ising Model QFT Operations spent on magic state distillation: 99.4% Operations spent on distillation (percentage) Common Kernel *Quantum Fourier Transform with size 100. Operations spent on magic state distillation: 99.8% T-gate Percentage
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MAGIC-STATE DISTILLATION
Block Code Distillation Factory T T p2 T p T T “Distillation Factory” T
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COMMUNICATION VIA BRAIDING
Distance does not matter.
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COMMUNICATION VIA BRAIDING
Crossing is prohibited.
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COMMUNICATION VIA BRAIDING
Fewer crossings?
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OBJECTIVE Mapping
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Our Techniques for Congestion Minimization
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TECHNIQUES Mapping
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Concatenate and Arrange
TECHNIQUES Concatenate and Arrange Cost of Permutation Step 78% 66% 48% 48% 28%
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Force-Directed Annealing
TECHNIQUES Force-Directed Annealing 1 Vertex-Vertex Attraction 2 Edge-Edge Repulsion 3 Magnetic Dipole Source:
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Vertex-Vertex Attraction
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FORCE-DIRECTED ANNEALING
Vertex-Vertex Attraction Calculated with cycle-by-cycle simulation
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Edge-Edge Repulsion
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FORCE-DIRECTED ANNEALING
Edge-Edge Repulsion
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Magnetic Dipole + + - - - + -
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FORCE-DIRECTED ANNEALING
Magnetic Dipole Rotation
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FORCE-DIRECTED ANNEALING
Valiant-Style Routing Intermediate hops
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Multi-Level Factories
RESULTS Multi-Level Factories 5.6x overhead reduction
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Conclusion Magic-state distillation extremely dominates most applications’ workloads. Surface code braiding circuits are difficult to execute. Circuit latency and edge crossings are strongly correlated. Force-directed annealing heuristics generate low-latency qubit mappings. Hierarchical stitching optimizes multi-level circuits
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Thank you! Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures. Ding, Y., Holmes, A., Javadi-Abhari, A., Franklin, D., Martonosi, M., & Chong, F. T. (2018). arXiv preprint arXiv:
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