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Coordination meeting Sept 24, 2009
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AsAd Status Technical spec almost complete Componants tests ADC DAC
Supply Monitoring FPGA
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ADC Data test pattern frame clock 25MHz and frequency of the output bit clock 150MHz.
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CDR Ready October 15 Cooling + EMC not yet defined Detector ZAP AsAd
To CoBo Cooling Mechanical 3 m. maximum Cold plate Shield Supply
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Planning
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Test…..! Not so easy…manpower.. Functionnal Local manpower AND
AGET T2K test Phase 1 Not so easy…manpower.. CENBG+GANIL+IRFU+MSU Basic version ML 507) hits AGET Phase 2 CENBG+GANIL+IRFU+MSU 4 AsAd + 1 CoBo Phase 3 Geographical distribution Does not help..
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