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18-447 Computer Architecture Lecture 30: In-memory Processing
Vivek Seshadri Carnegie Mellon University Spring 2015, 4/13/2015
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Goals for This Lecture Understand DRAM technology
How it is built? How it operates? What are the trade-offs? Can we use DRAM for more than just storage? In-DRAM copying In-DRAM bitwise operations
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DRAM Module and Chip
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Goals of DRAM Design Cost Latency Bandwidth Parallelism Power Energy
Reliability
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DRAM Chip Bank
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DRAM Cell – Capacitor Empty State Fully Charged State Logical “0”
1 Small – Cannot drive circuits 2 Reading destroys the state
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Sense Amplifier top enable Inverter bottom
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Sense Amplifier – Two Stable States
VDD en en VDD Logical “1” Logical “0”
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Sense Amplifier Operation
VT VDD VT > VB en dis VB
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Capacitor to Sense Amplifier
? en VDD en VDD
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DRAM Cell Operation Cell regains charge Cell loses charge ½VDD ½VDD+δ
dis en ½VDD
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Amortizing Cost – DRAM Tile
Row Driver
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DRAM Subarray Row Decoder Row Driver Tile Tile Tile
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DRAM Subarray Tile Tile Tile Tile Tile Tile Tile Row Decoder
Row Driver Tile Tile Tile Tile Tile Tile Tile
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Array of Sense Amplifiers (8Kb) Array of Sense Amplifiers
DRAM Bank Row Decoder Cell Array Array of Sense Amplifiers (8Kb) Cell Array Address Row Decoder Cell Array Array of Sense Amplifiers Cell Array Bank I/O (64b) Data Address
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Array of Sense Amplifiers (8Kb) Array of Sense Amplifiers
DRAM Chip Shared internal bus Row Decoder Array of Sense Amplifiers (8Kb) Cell Array Array of Sense Amplifiers Bank I/O (64b) Memory channel - 8bits
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Array of Sense Amplifiers
DRAM Operation Row Decoder 1 ACTIVATE Row Row Address 2 READ/WRITE Column Row Decoder Cell Array Array of Sense Amplifiers Cell Array 3 PRECHARGE Bank I/O Data Column Address
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Goals for This Lecture Understand DRAM technology
How it is built? How it operates? What are the trade-offs? Can we use DRAM for more than just storage? In-DRAM copying In-DRAM bitwise operations
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Trade-offs in DRAM Design
Cost Latency Bandwidth Parallelism Power Energy Reliability Rows/Subarray Data width, Chips/DIMM Banks/Chip
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Goals for This Lecture Understand DRAM technology
How it is built? How it operates? What are the trade-offs? Can we use DRAM for more than just storage? In-DRAM copying In-DRAM bitwise operations
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Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization
RowClone Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization Vivek Seshadri Put down “Vivek” Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. B. Gibbons, M. A. Kozuch, T. C. Mowry
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Memory Channel – Bottleneck
Limited Bandwidth Memory Core Cache Channel MC Core High Energy
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Goal: Reduce Memory Bandwidth Demand
Core Cache Channel MC Core Reduce unnecessary data movement
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Bulk Data Copy and Initialization
src dst Bulk Data Copy Bulk Data Initialization dst val
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Bulk Copy and Initialization – Applications
Zero initialization (e.g., security) Forking Checkpointing VM Cloning Deduplication Page Migration Many more
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Shortcomings of Existing Approach
High Energy (3600nJ to copy 4KB) Core Cache dst Channel MC src Core 1 micro second even with pipelining… High latency (1046ns to copy 4KB) Interference
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Our Approach: In-DRAM Copy with Low Cost
X High Energy Core Cache dst Channel MC ? src Core X High latency X Interference
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RowClone: In-DRAM Copy
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Bulk Copy in DRAM – RowClone
½VDD +δ ½VDD VDD Data gets copied 1 ½VDD
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Fast Parallel Mode – Benefits
Bulk Data Copy (4KB across a module) 11X 74X Latency Energy 1046ns to 90ns 3600nJ to 40nJ No bandwidth consumption Very little changes to the DRAM chip
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Fast Parallel Mode – Constraints
Location constraint Source and destination in same subarray Size constraint Entire row gets copied (no partial copy) Can still accelerate many existing primitives (copy-on-write, bulk zeroing) 1 Alternate mechanism to copy data across banks (pipelined serial mode – lower benefits than Fast Parallel) 2
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End-to-end System Design
Software interface memcpy and meminit instructions Managing cache coherence Use existing DMA support! Maximizing use of Fast Parallel Mode Smart OS page allocation
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Results Summary
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Goals for This Lecture Understand DRAM technology
How it is built? How it operates? What are the trade-offs? Can we use DRAM for more than just storage? In-DRAM copying In-DRAM bitwise operations
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Triple Row Activation C(A + B) + ~C(AB) Final State AB + BC + AC ½VDD
dis en ½VDD
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Throughput Results L1 L2 L3 Memory
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Goals for This Lecture Understand DRAM technology
How it is built? How it operates? What are the trade-offs? Can we use DRAM for more than just storage? In-DRAM copying In-DRAM bitwise operations
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