1. Solid State Electronics ECE-1109
Md. Ebtidaul KArim

2. Introduction FET( Field Effect Transistor) is a three terminal device.
Three terminal are drain , Gate and source.
FET is a voltage controlled device while BJT is a current control device( output characteristics are controlled by base current not base voltage).

3. Types There are two types of FET. Such as:
Junction Field Effect Transistor(JFET)
Metal Oxide Semiconductor Field Effect Transistor(MOSFET)
Again JFET are of two types. Such as:
n-channel JFET
p-channel JFET
MOSFET is again of two types. Such as:
Depletion type MOSFET
Enhancement type MOSFET.

4. JFET
JFET is a unipolar device depending solely on either electron(n-channel) or hole(p-channel) conduction.
For FET an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. As a result it is known as Field Effect Transistor.
It has high input impedance.
More temperature stable than BJT.
FET are usually smaller than BJT.

5. JFET Construction
n-channel JFET

6. JFET Construction
Major part of the structure is the n-type material, which forms the channel between the embedded layers of p-type material.
Top of the n-type channel is connected to a terminal known as Drain(D), whereas the lower end is connected to a terminal known as Source(S).
Two p-type materials are connected together to the Gate(G) terminal.
In the absence of any applied potential JFET has two p-n junctions under no bias condition.
As a result depletion region is developed at each junction similar to no bias condition of BJT.

7. JFET Construction Water Analogy of JFET:
“Gate” through an applied signal(potential), controls the flow of water(charge) to the “drain”.
Drain and source terminal are at the opposite end of the n-channel.

8. JFET Construction
p-channel JFET is almost similar to n-channel JFET except for the fact that here major part of the structure is p-type material.
p-channel JFET

9. JFET at 𝑉 𝐺𝑆 =0V and 𝑉 𝐷𝑆 positive
Here 𝑉 𝐷𝑆 is positive and gate is connected directly to source to get 𝑉 𝐺𝑆 =0V.
As gate and source is at same potential, depletion region at the lower end of each p-material is similar to the distribution of the no-bias conditions.
As we apply 𝑉 𝐷𝑆 = 𝑉 𝐷𝐷 electrons are drawn to the gate terminal. Here 𝐼 𝐷 = 𝐼 𝑆
Depletion region is wider at the top of the both p-type material.

10. JFET at 𝑉 𝐺𝑆 =0V and 𝑉 𝐷𝑆 positive
Current 𝐼 𝐷 establishes voltage level through the channel.
Here upper region of the p-type is reverse biased by 1.5 V and lower region with 0.5V only.
Greater the applied revered voltage, wider the depletion region.
As p-n junction is reversed bias here 𝐼 𝐺 =0𝐴

11. JFET at 𝑉 𝐺𝑆 =0V and 𝑉 𝐷𝑆 positive
As 𝑉 𝐷𝑆 increases, channel width decreases.
As a result resistance increases.
More horizontal the curve, higher the resistance.
As 𝑉 𝐷𝑆 increases there appears a state where two depletion region touches. It is called pinch-off.
The level of 𝑉 𝐷𝑆 for which it occurs is known as pinch-off voltage and is denoted by 𝑉 𝑃 .

12. JFET at 𝑉 𝐺𝑆 =0V and 𝑉 𝐷𝑆 = 𝑉 𝑝
Although pinch-off suggests that at pinch-off current 𝐼 𝐷 will be zero, but it is not true.
In reality a very small channel still exist, with a current of very high densities.
If 𝐼 𝐷 was zero then there will be loss of depletion region distributions that caused the pinch-off.

13. JFET at 𝑉 𝐺𝑆 =0V and 𝑉 𝐷𝑆 = 𝑉 𝑝
As 𝑉 𝐷𝑆 is increased beyond 𝑉 𝑃 , the region of close encounter between two depletion region increases in length along the channel, but 𝐼 𝐷 remains constant.
Here JFET acts as current source and current is fixed at 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 (Drain to source current with short circuit connection from source to gate. 𝐼 𝐷𝑆𝑆 is the maximum drain current for a JFET and is defined by the conditions: 𝑉 𝐺𝑆 =0𝑉 and 𝑉 𝐷𝑆 > 𝑉 𝑃

14. JFET at 𝑉 𝐺𝑆 <0

15. JFET at 𝑉 𝐺𝑆 <0
As we increase negative bias at 𝑉 𝐺𝑆 , saturation level is reached at lower 𝑉 𝐷𝑆 and resulting saturation level for 𝐼 𝐷 has been reduced.
Eventually at one stage 𝐼 𝐷 will be zero.
The level of 𝑉 𝐺𝑆 that results in 𝐼 𝐷 =0𝑚𝐴 is defined by 𝑉 𝐺𝑆 =− 𝑉 𝑃 , with 𝑉 𝑃 being a negative voltage for n-channel JFETs and positive voltage for p-channel JFETs.
Left side of pinch off region is known as ohmic or voltage controlled resistance region. I acts as a variable resistor, shoes resistance is controlled by 𝑉 𝐺𝑆 .
Here 𝑟 𝑑 = 𝑟 0 (1− 𝑉 𝐺𝑆 𝑉 𝑃 ) 2 , where 𝑟 0 is the resistance at 𝑉 𝐺𝑆 =0𝑉

16. p-Channel JFET
Here 𝑉 𝐷𝑆 is negative and gate is connected directly to source to get 𝑉 𝐺𝑆 =0V.
As gate and source is at same potential, depletion region at the lower end of each n-material is similar to the distribution of the no-bias conditions.
As we apply 𝑉 𝐷𝑆 = 𝑉 𝐷𝐷 electrons are drawn to the gate terminal. Here 𝐼 𝐷 = 𝐼 𝑆
Depletion region is wider at the top of the both n-type material due to more applied reverse bias.
Now if 𝑉 𝐺𝑆 is made positive, pinch off occurs at lower level of 𝑉 𝐷𝑆

17. p-Channel JFET
At high level of 𝑉 𝐷𝑆 , breakdown occurs and curve suddenly rises to levels that seem unbounded.
This may also occur for n-channel JFETs

18. JFET Symbols
The arrow at the gate terminals indicate the direction of current flow 𝐼 𝐺 if the p-n junctions were forward biased.

19. Transfer Characteristics
For BJT we get 𝐼 𝐶 =𝑓 𝐼 𝐵 =𝛽 𝐼 𝐵 , here linear relationship exists between 𝐼 𝐶 and 𝐼 𝐵 .
But the input output relationship of JFET is not linear.
Here, 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 (1− 𝑉 𝐺𝑆 𝑉 𝑃 ) 2 …(1)
When 𝑉 𝐺𝑆 =0𝑉, 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 …(a)
When 𝑉 𝐺𝑆 = 𝑉 𝑃 , 𝐼 𝐷 =0𝑚𝐴….(b)
We can write, 𝑉 𝐺𝑆 = 𝑉 𝑃 1− 𝐼 𝐷 𝐼 𝐷𝑆𝑆 ..(2)

20. Transfer Characteristics
Putting the value of 𝑉 𝐺𝑆 = 𝑉 𝑃 2 in (1) we get, 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 4 …..(c)
Again if we put 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 2 in (2) we get, 𝑉 𝐺𝑆 =0.3 𝑉 𝑃 ….(d)
Now putting the value of (a), (b), (c) and (d) in a table we get
𝑉 𝐺𝑆
𝐼 𝐷
𝐼 𝐷𝑆𝑆
0.3 𝑉 𝑃
𝐼 𝐷𝑆𝑆 2
0.5 𝑉 𝑃
𝐼 𝐷𝑆𝑆 4
𝑉 𝑃

21. n-Channel depletion-type MOSFET
There is no direct electrical connection between the gate terminal and the channel of the MOSFET.
Insulator Provides very high input impedance.

22. Depletion Type MOSFET

23. Depletion Type MOSFET
In Fig. 5.26, 𝑉 𝐺𝑆 has been set at a negative voltage such as -1 V.
The negative potential at the gate will tend to pressure electrons toward the p-type substrate (like charges repel) and attract holes from the p-type substrate (opposite charges attract).
Recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction.

24. Depletion Type MOSFET
The more negative the bias, the higher the rate of recombination.
The resulting level of drain current is therefore reduced with increasing negative bias for 𝑉 𝐺𝑆 as shown in next figure for 𝑉 𝐺𝑆 =−1 V, -2 V, and so on, to the pinch-off level of -6 V.
For positive values of 𝑉 𝐺𝑆 , the positive gate will draw additional electrons (free carriers) from the p-type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particle
As the gate-to-source voltage continues to increase in the positive direction, drain current will increase at a rapid rate.
The application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the channel compared to that encountered with 𝑉 𝐺𝑆 =0 V.

25. Depletion Type MOSFET
For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region, with the region between cutoff and the saturation level of 𝐼 𝐷𝑆𝑆 referred to as the depletion region
Drain and transfer characteristics for an n-channel depletion-type MOSFET

26. Depletion Type MOSFET p-Channel:
The construction of a p-channel depletion-type MOSFET is exactly the reverse of that of n-Channel depletion-type MOSFET.
There is now an n-type substrate and a p-type channel.
The terminals remain as identified, but all the voltage polarities and the current directions are reversed.
Here 𝑉 𝐷𝑆 is negative, 𝐼 𝐷 positive value and 𝑉 𝐺𝑆 polarity is reversed.

27. Depletion Type MOSFET p-Channel:
p-Channel depletion-type MOSFET with 𝐼 𝐷𝑆𝑆 =6 mA and 𝑉 𝑃 =+6 V

28. Depletion Type MOSFET Symbols:
The lack of a direct connection (due to the gate insulation) between the gate and channel is represented by a space between the gate and the other terminals of the symbol.
The vertical line representing the channel is connected between the drain and source and is “supported” by the substrate.
The arrow at the gate terminals indicate the direction of current flow 𝐼 𝐺 if the p-n junctions were forward biased.

29. Enhancement-type MOSFET
Basic Construction:
A slab of p-type material is formed from a silicon base and is referred to as the substrate.
The source and drain terminals are again connected through metallic contacts to n-doped regions, but note in the absence of a channel between the two n-doped regions.
This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs.
The Si 𝑂 2 layer is still present to isolate the gate metallic platform from the region between the drain and source.
n-Channel enhancement-type MOSFET.

30. Enhancement-type MOSFET
Basic Operation and Characteristics:
If 𝑉 𝐺𝑆 is set at 0 V and a voltage applied between the drain and source of the device the absence of an n-channel will result in a current of effectively zero amperes.
There are in fact two reverse-biased p-n junctions between the n-doped regions and the p-substrate to oppose any significant flow between drain and source.
Now both 𝑉 𝐷𝑆 and 𝑉 𝐺𝑆 have been set at some positive voltage greater than 0 V.
The positive potential at the gate will pressure the holes (since like charges repel) in the p-substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p-substrate

31. Enhancement-type MOSFET
Basic Operation and Characteristics:
The result is a depletion region near the SiO2 insulating layer void of holes.
However, the electrons in the p-substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer.
As 𝑉 𝐺𝑆 increases in magnitude, the concentration of electrons near the SiO2 surface increases until eventually the induced n-type region can support a measurable flow between drain and source.
The level of 𝑉 𝐺𝑆 that results in the significant increase in drain current is called the threshold voltage and is given the symbol 𝑉 𝑇 .

32. Enhancement-type MOSFET
Basic Operation and Characteristics:
Since the channel is nonexistent with 𝑉 𝐺𝑆 =0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET.
As 𝑉 𝐺𝑆 is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current.
However, if we hold 𝑉 𝐺𝑆 constant and increase the level of 𝑉 𝐷𝑆 , the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET.
How??
Increasing level of VDS for a fixed value of VGS

33. Enhancement-type MOSFET
Basic Operation and Characteristics:
Here 𝑉 𝐷𝐺 = 𝑉 𝐷𝑆 − 𝑉 𝐺𝑆
As we increase 𝑉 𝐷𝑆 by keeping 𝑉 𝐺𝑆 fixed, there is a reduction in gate to drain voltage.
This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers, causing a reduction in the effective channel width.
Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be established
Increasing level of VDS for a fixed value of VGS

34. Enhancement-type MOSFET
We see from the fig that, with 𝑉 𝐺𝑆 =8 V, saturation occurred at a level of 𝑉 𝐷𝑆 =6 V.
So we can write, 𝑉 𝐷𝑆 𝑠𝑎𝑡 = 𝑉 𝐺𝑆 − 𝑉 𝑇
Higher the level of 𝑉 𝐺𝑆 , the more the saturation level for 𝑉 𝐷𝑆 .
For levels of 𝑉 𝐺𝑆 > 𝑉 𝑇 , the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship:
𝐼 𝐷 =𝑘 ( 𝑉 𝐺𝑆 − 𝑉 𝑇 ) 2
The k term is a constant that is a function of the construction of the device.

35. Enhancement-type MOSFET
Transfer Characteristics:
The curve does not rise until 𝑉 𝐺𝑆 = 𝑉 𝑇

36. Enhancement-type MOSFET
p-Channel:
The construction of a p-channel enhancement-type MOSFET is exactly the reverse of n-channel enhancement-type MOSFET.
The terminals remain as identified, but all the voltage polarities and the current directions are reversed.

37. Enhancement-type MOSFET
p-Channel:
The transfer characteristics will be the mirror image (about the 𝐼 𝐷 axis) of the transfer curve

38. Enhancement-type MOSFET
Symbols:
The dashed line between drain and source was chosen to reflect the fact that a channel does not exist between the two under no-bias conditions.
The arrow at the gate terminals indicate the direction of current flow 𝐼 𝐺 if the p-n junctions were forward biased similar to depletion type MOSFET.

39. Maths
Boylestad:
V.K. Mehta:

40. Thank You