1. EE 5340 Semiconductor Device Theory Lecture 28 - Fall 2003
Professor Ronald L. Carter
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2. n-channel enhancement MOSFET in ohmic region
0< VT< VG
Channel
VS = 0
0< VD< VDS,sat
EOx,x> 0 n+
e-e- e- e- e- n+
Depl Reg
p-substrate
Acceptors
VB < 0
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3. Fully biased n- channel VT calc
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4. Fully biased p- channel VT calc
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5. “Dotted box” approx**
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6. Calculating xi and DVT
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7. MOS energy bands at Si surface for n-channel
Fig 8.10**
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8. If xi << xd,max calc. VT from effective DQ’ss
Fig 8.11**
|Q’d,max|/q (cm-2)
xd,max (microns)
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9. Flat band with oxide charge (approx. scale)
SiO2
p-Si
+<--Vox-->-
q(Vox)
Ec,Ox
q(ffp-cox)
q(fm-cox) Ex
Eg,ox~8eV
EFm Ec
EFi
EFp
q(VFB) Ev
VFB= VG-VB, when Si bands are flat Ev
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10. Fully biased n- channel VT calc
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11. If xi ~ xd,max
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12. Calculating VT
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13. Implanted VT Vt per Eq. 9.1.23 in M&K for a MOSFET with an
87-nm-thick gate oxide,
Qff/q = 1011 cm-2,
N’ = 3.5 X 1011 cm-2, and
Na = 2 X 1015 cm-3. Both
VS and VB =
Figure 9.8 (p. 441)
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14. Mobilities**
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15. M&K Fig (Eq )
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16. Mobilities**
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17. Subthreshold conduction
Below O.S.I., when the total band-bending < 2|fp|, the weakly inverted channel conducts by diffusion like a BJT.
Since VGS>VDS, and below OSI, then Na>nS >nD, and electr diffuse S --> D
Electron concentration at Source
Concentration gradient
driving diffusion
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18. M&K Fig.9.10 (p.443)
Band diagram along the channel region of an n-channel MOSFET under bias, indicating that the barrier qΦB at the source depends on the gate voltage.
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19. M&K Fig (p.444)
Measured subthreshold characteristics of an MOS transistor with a 1.2 μm channel length. The inverse slope of the straight-line portion of this semilogarithmic plot is called the drain-current subthreshold slope S (measured in mV/decade of drain current).
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20. Subthreshold current data
Figure 10.1**
Figure 11.4*
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21. Mobility variation due to Edepl
Figures 11.7,8,9*
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22. Velocity saturation effects
Figure 11.10*
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23. Final Exam For BOTH sections, 051 and 001 The Final is comprehensive
8:00 to 10:30 AM
Tuesday, December 9 in
206 ACT
Cover sheet on web page at
The Final is comprehensive
20% to 25% on Test 1 material
20% to 25% on Test 2 material
Balance of final on material since Test 2
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24. References
* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.
**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986
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