1. Dept of ECM Verilog HDL Verilog Evolution Verilog Attributes The verilog language Verilog Evolution  Verilog was designed in early 1984 by Gateway Design Automation  Gateway Design Automation and its Verilog-based tools were later acquired by Cadence Design System  In an effort for popularizing Verilog, in 1990, OVI (Open Verilog International) was formed and Verilog was placed in public domain  In 1993, efforts for standardization of this language started. Verilog became the IEEE standard, IEEE Std. 1364-1995, in 1995  A new version of Verilog was approved by IEEE in 2001. This version that is referred to as Verilog-2001

2. Dept of ECM Cont.. Verilog Attributes i.Switch level ii.Gate level iii.Pin-to-Pin delay iv.Bussing specifications v.Behavioral level vi.System utilities vii.Programming language interface (PLI) The verilog language

3. Dept of ECM Elements of Verilog Hardware Modules module module-name List of ports; Declarations... Functional specification of module... endmodule Primitive Instantiations module MultiplexerA (input a, b, s, output w); wire a_sel, b_sel, s_bar; not U1 (s_bar, s); and U2 (a_sel, a, s_bar); and U3 (b_sel, b, s); or U4 (w, a_sel, b_sel); endmodule

4. Dept of ECM Cont.. Assign statements Condition expressions Procedural blocks Module instantiations module MultiplexerD (input a, b, s, output w); reg w; always @ (a, b, s) begin if (s) w = b; else w = a; end endmodule module MultiplexerC (input a, b, s, output w); assign w = s ? b : a; endmodule module ANDOR (input i1, i2, i3, i4, output y); assign y = (i1 & i2) | (i3 & i4); endmodule module MultiplexerE (input a, b, s, output w); wire s_bar; not U1 (s_bar, s); ANDOR U2 (a, s_bar, s, b, w); endmodule

5. Dept of ECM RT Level Design

6. Dept of ECM Component description in verilog Data components Multiplexer Flip-Flop Counter Full adder Shift register ALU Interconnections Controllers Synchronizer Sequence detector