1. Initial Estimates and Results of Cell Sizing
STT-RAM Project
Initial Estimates and
Results of Cell Sizing

2. Expected MTJ Parameters (Ilya/Pedram)
I-STT
RP ≈ Ω
TMR ≈ %
Lowest write energy:
VWRITE ≈ 0.6-1V
tPULSE ≈ 1-5ns
C-STT
RP ≈ Ω
TMR ≈ 30-50%
VWRITE ≈ V
tPULSE ≈ ns

3. Reference SRAM Cell For IBM65: F = 0.1μm SRAM Size: 0.625μm2 = 62.5F2

4. STT-RAM Cell Sizing
For a 2 finger device, cell area is approx: 0.61μm x (WFINGER + 0.2μm)
50F2 → 620nm/50nm x2
35F2 → 380nm/50nm x2
25F2 → 220nm/50nm x2
27.5 F2
(OLD CELLS)
52.5 F2

5. I-STT Results for “Balanced” Voltage
VWL = 1.0V
VDD = 1V; RP ≈ Ω; TMR ≈ %
VWL = 1.2V (15-40% increase in IWRITE/VWRITE)
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2

6. I-STT Results for “Balanced” Current
VWL = 1.0V
VDD = 1V; RP ≈ Ω; TMR ≈ %
VWL = 1.2V (15-40% increase in IWRITE/VWRITE)
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2

7. C-STT Results for “Balanced” Voltage
VWL = 1.0V
VDD = 1V; RP ≈ Ω; TMR ≈ 30-50%
VWL = 1.2V (15-40% increase in IWRITE/VWRITE)
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2

8. C-STT Results for “Balanced” Current
VWL = 1.0V
VDD = 1V; RP ≈ Ω; TMR ≈ 30-50%
VWL = 1.2V (15-40% increase in IWRITE/VWRITE)
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2
IAP→P [μA]
IP→AP [μA]
50F2
35F2
25F2
VAP→P [mV]
VP→AP [mV]
50F2
35F2
25F2