1. Floorplanning (Adapted from Prof. E. Young’s and Prof. Y
Floorplanning (Adapted from Prof. E. Young’s and Prof. Y.-W Chang’s notes)

2. Hierarchical Design Blocks are obtained after partitioning: Need to:
Put the blocks together.
Design each block.
Which step to go first?

3. Hierarchical Design
How to put the blocks together without knowing their shapes and I/O pin positions (they are not designed yet)?
If we design the blocks first, those blocks may not be able to form a tight packing.

4. Floorplanning
The floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize circuit performance:
chip area
total wire length
delay of critical path
routability
others, e.g., noise, heat dissipation, etc.

5. Floorplanning v.s. Placement
Both determines block positions to optimize the circuit performance.
Floorplanning:
Details like shapes of blocks, I/O pin positions, etc. are not yet fixed (blocks with flexible shape are called soft blocks).
Placement:
Details like module shapes and I/O pin positions are fixed (blocks with no flexibility in shape are called hard blocks).

6. Floorplanning Problem
Input:
n Blocks with areas A1, ... , An
Bounds ri and si on the aspect ratio of block Bi
Output:
Coordinates (xi, yi), width wi and height hi for each block such that hi wi = Ai and ri  hi/wi  si
Objective:
To optimize the circuit performance.

7. Bounds on Aspect Ratios
If there is no bounds on the aspect ratios, we can surely pack very tightly:
But we don’t want to layout blocks as long strips, so we require ri  hi/wi  si for each i.

8. Bounds on Aspect Ratios
We can also allow several shapes for each block:
For some hard blocks, the orientations can be changed:

9. Objective Function
A commonly used objective function is a weighted sum of area and wire length:
cost = aA + bL
where A is the total area of the packing, L is the total wire length, and a and b are constants.

10. Wire Length Estimation
Exact wire length of each net is not known until routing is done.
In floorplanning, even pin positions are not known yet.
Some possible wire length estimations:
Center-to-center estimation
Half-perimeter estimation

11. Dead Space Dead space is the space that is wasted:
Minimizing area is the same as minimizing dead space.
Dead space percentage is computed as
(A - iAi) / A  100%
Dead space

12. Analytical Approach
The floorplanning problem can be formulated as a mixed integer linear program.

13. MILP Problem Formulation
Minimize the packing area:
Assume that one dimension W is fixed.
Minimize the other dimension Y.
Need to have constraints
so that blocks do not overlap.
Associate each block Bi with 4 variables:
xi and yi: coordinates of its lower left corner.
wi and hi: width and height. W Y

14. Non-overlapping Constraints
For two non-overlapping blocks Bi and Bj, at least one of the following four linear constraints must be satisfied: hi Bi hj Bj
(xi, yi) wi
(xj, yj) wj

15. Integer Variables Use integer (0 or 1) variables xij and yij:
xij=0 and yij =0 if (1) is true.
xij=0 and yij =1 if (2) is true.
xij=1 and yij =0 if (3) is true.
xij=1 and yij =1 if (4) is true.
Let W and H be upper bounds on the total width and height. Non-overlapping constraints:

16. Formulation

17. Formulation with Hard Blocks
If the blocks can be rotated, use a 0-1 integer variable zi for each block Bi s.t. zi = 0 if Bi is in the original orientation and zi = 1 if Bi is rotated 90o .

18. Formulation with Soft Blocks
If Bi is a soft block, wihi=Ai. But this constraint is quadratic!
Linearized by taking the first two terms of the Taylor expression of hi=Ai/wi at wimax (max. width of block Bi).
hi =himin+li(wimax-wi)
where himin =Ai/wimax and li=Ai/wimax2

19. Formulation with Soft Blocks
If Bi is soft and Bj is hard:
If both Bi and Bj are soft:

20. Complexity
For a problem with n blocks, and for the simplest case, i.e., all blocks are hard:
4n continuous variables (xi, yi, wi, hi)
n(n-1) integer variables (xij, yij)
2n2 linear constraints
Practically, this method can only solve small size problems.

21. Successive Augmentation
A classical greedy approach to keep the problem size small: repeatedly pick a small subset of blocks to formulate a MILP, solve it together with the previously picked blocks with fixed locations and shapes:
next subset Y
partial solution

22. Generic Simulated Annealing Algorithm
1 begin
2 Get an initial solution S;
3 Get an initial temperature T > 0;
4 while not yet “frozen” do
5 for 1  i  P do
Pick a random neighbor S' of S;
  cost(S') - cost(S);
/* downhill move */
if   0 then S  S'
/* uphill move */
if  > 0 then S  S' with probability ;
10 T  rT; /* reduce temperature */
11 return S
12 end

23. Simulated Annealing Approach
Many floorplanning tools are based on simulated annealing.
In simulated annealing, we need to have a good representation for each candidate floorplan solution.
There are three kinds of floorplan: slicing, mosaic and non-slicing.

24. Slicing Floorplan
A floorplan that can be obtained by recursively cutting a rectangle into two by either a vertical line or a horizontal line:

25. Non-Slicing Floorplan
Any general floorplan which is not necessarily obtained by recursively dividing rectangles.
empty room

26. Mosaic Floorplan A floorplan that:
Divided into rooms and every room is occupied.
Every module corner (except those at the four corners of the chip) is formed by a T-junction.
The non-crossing segment of a T-junction can slide along the crossing segment: 

27. Mosaic Floorplan
No empty room.

28. P-admissible Representation
A packing representation is P-admissible if:
The solution space is finite.
Every solution corresponds to a feasible packing.
Evaluation for each solution, i.e., computing the cost value, is possible in polynomial time, and so is the realization of the corresponding packing.
The optimal packing is included in the solution space and corresponds to the one with the best evaluated cost value.

29. Slicing Floorplan Representation
“A New Algorithm for Floorplan Design”, D.F. Wong and C.L. Liu, Design Automation Conference, 1986, pages

30. Slicing Floorplan Structure
Rectangular dissection: Subdivision of a given rectangle by a finite # of horizontal and vertical line segments into a finite # of non-overlapping rectangles.
Slicing structure: a rectangular dissection that can be obtained by repetitively subdividing rectangles horizontally or vertically.
Slicing tree: A binary tree, where each internal node represents a vertical cut line or horizontal cut line, and each leaf a basic rectangle.
Skewed slicing tree: One in which no node and its right child are the same.

31. Solution Representation
An expression E = e1 e2… e2n-1, where ei  {1, 2, …, n, H, V}, 1  i  2n-1, is a (Reverse) Polish expression of length 2n-1 iff
every operand j, 1  j  n, appears exactly once in E;
(the balloting property) for every subexpression Ei = e1 … ei, 1  i  2n-1, # operands > # operators.
Polish expression  Postorder traversal.
ijH: rectangle i on bottom of j; ijV: rectangle i on the left of j.

32. Redundant Representation

33. Normalized Polish Expression
A Polish expression E = e1 e2 … e2n-1 is called normalized iff E has no consecutive operators of the same type (H or V).
Given a normalized Polish expression, we can construct a unique rectangular slicing structure.

34. Neighborhood Structure
Chain: HVHVH … or VHVHV …
Adjacent: 1 and 6 are adjacent operands; 2 and 7 are adjacent operands; 5 and V are adjacent operand and operator.
3 types of moves:
M1 (Operand Swap): Swap two adjacent operands.
M2 (Chain Invert): Complement some chain (V = H, H = V).
M3 (Operator/Operand Swap): Swap two adjacent operand and operator.

35. Effects of Perturbation1 2 3 4
Question: The balloting property holds during the moves?
M1 and M2 moves are OK.
Check the M3 moves! Reject “illegal” M3 moves.
Check M3 moves: Assume that M3 swaps the operand ei with the operator ei+1, 1  i  k-1. Then, the swap will not violate the balloting property iff 2Ni+1 < i.
Nk: # of operators in the Polish expression E = e1 e2 … ek, 1  k  2n-1

36. Cost Function  = A +  W. W= ijcij dij.
A: area of the smallest rectangle
W: overall wiring length
 : user-specified parameter
W= ijcij dij.
cij: # of connections between blocks i and j.
dij: center-to-center distance between basic rectangles i and j. 1 2 3 4

37. Area Computation for Hard Blocks
Allow rotation
Wiring cost?
Center-to-center interconnection length

38. Incremental Computation of Cost Function
Each move leads to only a minor modification of the Polish expression.
At most two paths of the slicing tree need to be updated for each move.

39. Incremental Computation of Cost Function (cont'd)

40. Annealing Schedule Initial solution: 12V3V … nV.
Ti = ri T0, i = 1, 2, 3, …; r =0.85.
At each temperature, try kn moves (k = 5-10).
Terminate the annealing process if
# of accepted moves < 5%,
temperature is low enough, or
run out of time.

41. Shape Curve for Floorplan Sizing
A soft (flexible) blocks b can have different aspect ratios, but is with a fixed area A.
The shape function of b is a hyperbola: xy = A, or y =A/x, for width x and height y.
Very thin blocks are often not interesting and feasible to design
Add two straight lines for the constraints on aspect ratios.
Aspect ratio: r  y/x  s.
y = sx
y = rx
legal
shapes y x x y

42. Shape Curve
Since a basic block is built from discrete transistors, it is not realistic to assume that the shape function is smooth
In an extreme case, a block is rigid/hard: it can only be rotated and mirrored during floorplanning or placement
feasible
region y x
The shape curve of a 2  4 hard block.

43. Shape Curve (cont’d)
In general, a piecewise linear function can be used to approximate any shape function.
The points where the function changes its direction, are called the corner (break) points of the piecewise linear function. y x

44. Feasible Implementations
Shape curves correspond to different kinds of constraints where the shaded areas are feasible regions.

45. Slicing Floorplan Sizing
The shape functions of all leaf blocks are given as piecewise linear functions.
Traverse the slicing tree to compute the shape functions of all composite blocks (bottom-up composition).
Choose the desired shape of the top-level block
Only the corner points of the function need to be evaluated for area minimization.
Propagate the consequences of the choice down to the leaf blocks (top-down propagation).
The sizing algorithm runs in polynomial time for slicing floorplans
NP-complete for non-slicing floorplans

46. Non-Slicing Floorplan Representation
“Rectangle-Packing-Based Module Placement”, H. Murata, K. Fujiyoushi, S. Nakatake and Y. Kajitani, IEEE International Conference on Computer-Aided Design, 1995, pp
(Follow-up work: “FAST-SP: A Fast Algorithm for Block Placement on Sequence Pair”, X. Tang and D.F. Wong, ASP-DAC 2001, pp )

47. Sequence Pair (SP)
A floorplan is represented by a pair of permutations of the module names:
e.g
A sequence pair (s1, s2) of n modules can represent all possible floorplans formed by the n modules by specifying the pair-wise relationship between the modules
Solution space: (n!)2

48. Loci of module b

49. Relative Module Positions
A floorplan is a partition of a chip into rooms, each containing at most one block.
Locus (right-up, left-down, up-left, down-right)
Take a non-empty room.
Start at the center of the room, walk in two alternating directions to hit the sides of rooms.
Continue until to reach a corner of the chip.
Positive locus +: Union of right-up locus and left-down locus.
Negative locus -: Union of up-left locus and down-right locus.

50. Geometrical Information
No pair of positive (negative) loci cross each other, i.e., loci are linearly ordered.
SP uses two sequences (+, -) to represent a floorplan.
H-constraint: (..a..b.., ..a..b..) iff a is on the left of b
V-constraint: (..a..b..,..b..a..) iff b is below a
(+, -) = (abdecf, cbfade)

51. Floorplan Realization
Floorplan realization is the step to construct a floorplan from its representation.
How to construct a floorplan from a sequence pair?
We can make use of the horizontal and vertical constraint graphs (Gh and Gv).

52. Floorplan Realization
Whenever we see (…A…B…, …A…B…), add an edge from A to B in Gh with weight wA.
Whenever we see (…A…B…, …B…A…), add an edge from B to A in Gv with weight hA.
Add a source vertex s to Gh (and Gv) pointing, with weight 0, to all vertices without incoming edges.
Finally, find the longest paths from s to every vertex in Gh and Gv, which are the coordinates of the lower left corner of the module in the packing.

53. Example Gh
1.1 3 2
1.2 1
1.2
1.1
1.1 1
1.2 3 2
1.2 1 5
1.2 s
2.4 2 4 5 Gv 2 3 2 4 1 1 2 1
2.4
1.2 1 1 5
(13245,41352 ) 4 s

54. Cost Evaluation
Optimal (+, -)-Packing can be obtained in O(n2) time by applying a longest path algorithm on a vertex-weighted directed acyclic graph.
GH and GV are independent.
The X and Y coordinates of each module are the minimum values of the longest path length between s and the corresponding vertex in GH and GV, respectively.
Cost evaluation can be done in O(n lg lg n) time by computing the longest common subsequence of the two sequences (Tang & Wong, DATE-2K, ASP-DAC-01)

55. Moves Three kinds of moves in the annealing process:
M1: Rotate a module, or change the shape of a
module
M2: Interchange 2 modules in both sequences
M3: Interchange 2 modules in a sequence

56. Pros and Cons of SP Advantages: Disadvantages: Simple representation
All floorplans can be represented.
The solution space is finite. (How big?)
Disadvantages:
Redundant representation. The representation is not 1-to-1.
The size of the constraint graphs, and thus the runtime to construct the floorplan, is quadratic.

57. B*-Tree: Compacted Floorplan Representation
Chang et. al., “B-tree: A new representation for non-slicing floorplans,” DAC-2k.
Compact modules to left and bottom.
Construct an ordered binary tree (B*-tree).
Left child: the lowest, adjacent block on the right (xj = xi + wi).
Right child: the first block above, with the same x-coordinate (xj = xi). n0 b5 b6 b9 b5 b6 b9 b3 b3 n7 n1 b1 b1 b4 b4 b2 b2 n8 n2 n5 b0 b0 b8 b8 n9 n3 n6 b7 b7 n4
A non-slicing floorplan
Compact to left and down
B*-tree

58. B*-tree Packing x-coordinates can be determined by the tree structure.
Left child: the lowest, adjacent block on the right (xj = xi + wi).
Right child: the first block above, with the same x-coordinate (xj = xi).
y-coordinates? b7 b9 b8
b11
b10 b0 b1 b5 b2 b4 b6 b3
x7=x0+w0
x1=x0
(x0,y0) w0 n0 n2 n5 n3 n1 n4 n6 n8 n9 n7
n10
n11
The B*-tree keeps the geometric relationship between two modules as follows. If node nj is the left child of node ni, module bj must be located on the right-hand side and adjacent to module bi in the placement; therefore, xj is equal to xi plus wi. For instance, x7 is equal to x0 plus w0.
If node nj is the right child of ni, module bj must be located above and adjacent to module bi, with the x-coordinate of bj equal to that of bi; therefore xj is equal to xi. For example, x1 is is equal to x0.
We can determinate the x-coordinates from the tree structure, but how about the y-coordinates? CLICK

59. Computing y-coordinates
Horizontal contour: Use a doubly linked list to record the current maximum y-coordinate for each x-range
Reduce the complexity of computing a y-coordinate to amortized O(1) time
horizontal contour
b10 b3
vertical contour b1 b4
To compute the size of the bounding rectangle in the y direction, we may apply a contour data structure presented in the O-tree. By using the contour structure, we can compute a y-coordinate in linear time. We have a horizontal contour In the horizontal direction, similarly, we also have a vertical contour.
After adding a new module on top, CLICK we can search the horizontal contour from left to right and update it with the top boundary of the new module. CLICK b0 b9 b8
b11 b7

60. B*-Tree Perturbation Op1: rotate a macro Op2: delete & insert
Op3: swap 2 nodes
Op4: resize a soft macro
Op3(n1, n7)
Op2(n11, n6) n0 n0 n2 n5 n3 n1 n4 n6 n8 n9 n7
n10
n11 n0 n2 n5 n3 n4 n6 n8 n9 n7
n10
n11 n1 n1 n7 n8 n2 n5 n9 n3 n6
n10 n4
n11