1. ECE/CS 352 Digital Systems Fundamentals
Spring 2001
Chapter 4 – Part 5
Dr. Anthony DeGregoria and I would like to thank WIN Foundation and the Wisconsin Venture Network for the opportunity present to you today.
Tom Kaminski & Charles R. Kime
ECE/CS 352 Digital System Fundamentals

2. ECE/CS 352 Digital System Fundamentals
Overview of Chapter 4
Types of Sequential Circuits
Storage Elements
Latches
Flip-Flops
Sequential Circuit Analysis
State Tables
State Diagrams
Sequential Circuit Design
Specification
Assignment of State Codes
Implementation
HDL Representation
ECE/CS 352 Digital System Fundamentals

3. Sequential Circuit Implementation
ECE/CS 352 Digital System Fundamentals

4. ECE/CS 352 Digital System Fundamentals
State Coding – Example 1
How may assignments of codes with a minimum number of bits?
2 – A = 0, B = 1 or A = 1, B = 0
Does it make a difference?
Only in variable inversion, so small if any.
ECE/CS 352 Digital System Fundamentals

5. ECE/CS 352 Digital System Fundamentals
State Coding – Example 2
How may assignments of codes with a minimum number of bits?
4  3  2  1 = 24
Does code assignment make a difference?
See Next Two Slides
ECE/CS 352 Digital System Fundamentals

6. ECE/CS 352 Digital System Fundamentals
State Coding – Example 2
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 0
1 1 1
Code 1: A = 0 0, B = 0 1, C = 1 0, D = 1 1
See Next Slide
ECE/CS 352 Digital System Fundamentals

7. ECE/CS 352 Digital System Fundamentals
State Coding – Example 2
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 1
1 0 1
Code 2: A = 0 0, B = 0 1, C = 1 1, D = 1 0
So it does make a difference in cost!
ECE/CS 352 Digital System Fundamentals

8. ECE/CS 352 Digital System Fundamentals
Implementation
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 1
1 0 1
Using code 2:
ECE/CS 352 Digital System Fundamentals

9. Implementation with DFF
Present State
Next State
x = 0 x = 1
DFFY1
DFFY2
0 0
0 1 1
1 1
1 0
Using D = Q(t+1):
ECE/CS 352 Digital System Fundamentals

10. ECE/CS 352 Digital System Fundamentals
DFF Schematic
ECE/CS 352 Digital System Fundamentals

11. Implementation with TFF
Present State
Next State
x = 0 x = 1
TFFY1
TFFY2
0 0
0 1 1
1 1
1 0
Using T = Q(t)  Q(t+1)
ECE/CS 352 Digital System Fundamentals

12. Implementation with JKFF
ECE/CS 352 Digital System Fundamentals

13. Implementation with JKFF (Cont.)
ECE/CS 352 Digital System Fundamentals

14. Implementation with JKFF (Cont.)
Present State
Next State
x = 0 x = 1
JY1
KY1
0 0
0 1 X
1 1 1
1 0
ECE/CS 352 Digital System Fundamentals

15. RS Flip-Flop Implementation
ECE/CS 352 Digital System Fundamentals

16. RS Implementation (Cont.)
Present State
Next State
x = 0 x = 1
SY1
RY1
0 0
0 1 X
1 1 1
1 0
ECE/CS 352 Digital System Fundamentals

17. Sequential Logic Design Process
ECE/CS 352 Digital System Fundamentals

18. Second Example – Register File Cell: State Diagram Design
Make the state unchanged (Hold Reg) by adding all unused input combinations for each state.
CLS,LDS,Data_in
State/Data_out(i)
0, 1, 0; 1, -, -
0, 1, 1
RESET
A/0
B/1
0,1,0; 1,-,-; 0,0,-
0,1,1; 0,0,-
ECE/CS 352 Digital System Fundamentals

19. ECE/CS 352 Digital System Fundamentals
Second Example – Register File Cell: State Table – State Assignment (A=0, B=1)
Input:
State:
000
001
010
011
100
101
110
111
Output A B 1
Input:
State:
000
001
010
011
100
101
110
111
Output 1
ECE/CS 352 Digital System Fundamentals

20. ECE/CS 352 Digital System Fundamentals
DFF Implementation
Moving State Table Data to a K-Map and Solving: Q
LDS
Data_in
CLS 1
ECE/CS 352 Digital System Fundamentals

21. ECE/CS 352 Digital System Fundamentals
JKFF Implementation
Moving State Table Data to a K-Map and solving:
LDS
LDS KQ X X X X JQ 1 X X X X
CLS
CLS 1 1 1 1 X X Q X X Q 1 X X X X
Data_in
Data_in
ECE/CS 352 Digital System Fundamentals

22. Review: Excitation Tables
ECE/CS 352 Digital System Fundamentals