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CS 444/544 Operating Systems II Virtual Memory Translation

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Presentation on theme: "CS 444/544 Operating Systems II Virtual Memory Translation"— Presentation transcript:

1 CS 444/544 Operating Systems II Virtual Memory Translation
Yeongjin Jang 04/11/19

2 Recap: CR3 NOT This is the Segmentation a virtual to physical
translation Segmentation Access GDT Base,Limit Translate to Linear Addr Paging CR3 – points to page directory Higher 20 bits of the address Page number Highest 10 bits: Page Directory Index (PDX) CR3 == pgdir, pgdir[PDX(va)] Next 10 bits: Page Table Index (PTX) pgdir[PDX(va)] == pgtbl Pgtlb[PTX(va)] == PTE Page table Entry Highest 20 bits: Physical Page Number Lower 12 bits: Offset CR3[PDX(va)][PTX(va)] = PTE! This is the Virtual-physical Translation layer…

3 Recap – Page Table & Addr Translation
31 12 Virtual Physical 0x 0x10000 0x 0x11000 0x804a000 0x50000 0x Page number (20-bits) 0x08048 Offset (12-bits) 0x000 CR3[0x20] Directory Index (10-bits) 0x20 Table index (10-bits) 0x48 31 22 12 Phy. Page number (20-bits) 0x10000 Offset (12-bits) 0x000 Page Directory Entry Addr PT .. 0x20 0x3ff Page Table Entry Addr PT 0x48 0x10000 0x49 0x11000 0x4a 0x50000 PDE[0x48]

4 Recap – Page Table & Addr Translation
31 0x Page number (20-bits) 0x12345 Offset (12-bits) 0x678 In Python.. Directory Index (10-bits) 0x48 Table index (10-bits) 0x345 Lower 10 bits 31 22 12 Upper 10 bits

5 Page Table Lookup Access example Memory access sequence
Vritual Page number (20-bits) 0x12345 Offset (12-bits) 0x678 Page Table Lookup Access example movl 0x , %eax (load 4-byte data from the address 0x to %eax) Memory access sequence Virtual page number: top 20bits, PGNUM = (0x >> 12) = 0x12345 Page Directory Index: top 10 bits, PDX = ( PGNUM >> 10 )& 0x3ff = 0x48 Page Table Index: next 10 bits, PTX = PGNUM & 0x3ff = 0x345 Page Table Entry: PTE = CR3[PDX][PTX] – 2 memory dereferences Physical address = Physical Page Number + OFFSET = (PTE & 0xfffff000) + (0x & 0xfff) eax = PHY_ADDR[0] – 1 memory dereferences (required) Physical Page number (20-bits) 0x10000 Offset (12-bits) 0x678

6 Recap – Page Table & Addr Translation
31 12 Virtual Physical 0x 0x10000 0x 0x11000 0x804a000 0x50000 0x Page number (20-bits) 0x08048 Offset (12-bits) 0x000 Mem access #1 CR3[0x20] Directory Index (10-bits) 0x20 Table index (10-bits) 0x48 31 22 12 Phy. Page number (20-bits) 0x10000 Offset (12-bits) 0x000 Page Directory Entry Addr PT .. 0x20 0x3ff Page Table Entry Addr PT 0x48 0x10000 0x49 0x11000 0x4a 0x50000 Mem access #3 (required) PDE[0x48] Mem access #2

7 Page Table Lookup - Caching
Access example movl 0x , %eax 3 memory access per each memory access – SLOW! 2 additional accesses due to page table lookup mov instruction – takes 1 cycle memory access – takes ~200 cycles… 200 (access the address) + 1 (mov) * 2 (page table…) = 601 cycles.. CPU caches Address Translation Translation Lookaside Buffer (TLB) Reduce these additional accesses -> Speed up!

8 Translation Lookaside Buffer (TLB)
Stores VA-PA mappings and cache them! Benefits Do not have to walk down page tables for cached entries VPN (Virt Page Number) PPN (Phy Page Number) Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x > 0x678 0x > 0x5678 0x > 0xff678 0x > 0xfff678

9 CPU that does not have TLB
Page Directory Entry Addr PT .. 0x48 0x3ff CR3 Page Table Entry Addr PT 0x345 0x10000 0x346 0x11000 0x347 0x50000 0x 0x

10 CPU with TLB No page table access.. 0x10000000 VPN (Virt Page Number)
PPN (Phy Page Number) Valid 0x12345 0x10000 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff CPU Page Directory Entry Addr PT .. 0x20 0x3ff CR3 Page Table Entry Addr PT 0x48 0x10000 0x49 0x11000 0x4a 0x50000 0x 0x No page table access..

11 Address Translation with TLB (hit)
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff Hit! Access TLB 0x678! Address 0x

12 Address Translation with TLB (miss)
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff Access TLB Address 0x TLB miss Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG

13 Address Translation with TLB (miss)
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Access TLB Address 0x Add an entry! TLB miss Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG

14 Address Translation with TLB (hit)
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Access TLB Address 0x Hit! 0x0x101678! Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG

15 Why do we have TLB? Core i7-6700K (Skylake, 4.00 GHz)
TLB hit requires 4 cycles, 1ns!

16 Why do we have TLB? TLB hit requires 4 cycles, 1ns!
Page table walk requires 2 memory access for translation Uncached: 9 cycles + (42 cycles + 51ns) * 2 [TLB miss] [RAM latency] 2ns (10ns + 51ns) * = 124ns (124 times slower…) Cached: * 2 = 17 cycles if all blocks cached in L1 (4 ns, 4 times slower!)

17 We have limited entries in TLB
Core i7-6700K (Skylake, 4.00 GHz) 64 items for L1 d-TLB, 1536 items for L2 d-TLB CPU need to schedule this cache Based on Temporal/Spatial locality…

18 TLB Replacement Policy
Smart: LRU (Least Recently Used) Mark when the block was accessed (update timestamp upon access) When an eviction is required, evict the one with the oldest timestamp Random Do not do anything when accessed When an eviction is required, evict an entry randomly… Sometimes, this works better than LRU.. We will learn more about such scheduling later When we learn about process scheduling…

19 Synchronizing TLB with Page Table
CPU uses the TLB for caching Page Table Entries What will happen if content in TLB mismatches to the PTE in the page table? Access wrong physical memory… Does not honor the correct privilege in PTE (if we updated PTE after caching) Running a new process with new CR3 Use old process’s mapping, wrong access

20 TLB and Page Table Update
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Address 0x Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG

21 TLB and Page Table Update
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Address 0x Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x102 | FLAG Update

22 TLB and Page Table Update
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Address 0x We need to invalidate this entry Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x102 | FLAG Update

23 TLB and Process Context Switch
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Address 0x CR3 Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG

24 TLB and Process Context Switch
VPN PPN Valid 0x12345 0x0 1 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Address 0x CR3 Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0x20 | FLAG 0x348 0x30 | FLAG 0x349 0x50 | FLAG

25 TLB and Process Context Switch
VPN PPN Valid 0x12345 0x0 0x12346 0x5 0x12347 0xff 0x12348 0xfff 0x12349 0x101 Address 0x We need to invalidate all previous entries.. CR3 Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0xff | FLAG 0x348 0xfff | FLAG 0x349 0x101 | FLAG Page Directory Entry Addr PT .. 0x48 0x3ff Page Table Entry Addr PT 0x347 0x20 | FLAG 0x348 0x30 | FLAG 0x349 0x50 | FLAG

26 Updating Page Table When updating a Page Table Entry
We must invalidate TLB for that entry invlpg

27 Updating Page Table In JOS (kern/pmap.c & inc/x86.h)

28 Manipulating Page Tables in JOS
PGNUM(x) Get the page number (x >> 12) of the address x PDX(x) Get the page directory index (top 10 bits) of the address x PTX(x) Get the page table index (mid 10 bits) of the address x PGOFF(x) Get the page offset (lower 12 bits) of the address x

29 Manipulating Page Tables in JOS
PTE_ADDR(pte) Get the physical address that a pte points PTE_ADDR(pte) + PGOFF(x) The physical address pointed by the PTE, translated by a virtual address x Translate a virtual address va to physical address pa pte = CR3[PDX(va)][PTX(va)] pte_t **cr3 = lcr3(); # or, kern_pgdir pte_t *pt = cr3[PDX(va)] pte_t pte = pt[PTX(va)] physaddr_t pa = PTE_ADDR(pte) + PGOFF(va);

30 Pros/Cons of Segmentation
Easy implementation (in hardware) Select [Base address] and add offset Small memory requirement 8 byte for address translation in GDT (per each region) Can allocate by the exact size (within 20bits limit) Base = 0x10000, limit = 0x10 Memory protection (DPL)

31 Pros/Cons of Segmentation
Fragmentation Must allocate contiguous space for the region Need to search for such region (regarding size) Free: need to consolidate free memory chunks, etc.. Memory protection placed for the entire region… Program Code (160KB) 0x10000 ~ 0x38000 (64KB ~ 224KB) Program Data (64 KB) 0x58000 ~ 0x68000 (352KB ~ 416KB) Free (128 KB) 0x38000 ~ 0x58000 (224KB ~ 352KB) Program Code - 2 (160KB)

32 Pros/Cons of Paging Pros
Virtual Memory Physical Memory Stack 0xbffdf000 Pros No fragmentation (splitted by 4KB each blocks) Not requiring allocating contiguous space 0x > 0x10000 0x > 0xff000 0x804a000 -> 0xe0000 Fast allocation No need to search available blocks (just checks how many pages are available) Free: removing PTE! Memory protection can be enforced in page granularity Part of region could have a different protection bits Program code 0x14000 Program code 0x804a000 Program code 0x Stack 0x12000 Program code 0x Program code 0x11000 Program code 0x10000

33 Pros/Cons of Paging Cons Internal fragmentation – wasting memory
Requiring 1 byte – allocate 4KB Required 10 byte – allocate 4KB… Storing a Page Table 4MB for the full page table At least 8KB (2 pages, one for PD and the other one for PT) is required… Page table lookup for translation Slow, requires a more complex hardware than segmentation

34 Summary Address translation Segmentation – Pros/Cons
Segmentation: base+offset -> linear address Paging: virtual -> physical Segmentation – Pros/Cons Paging – Pros/Cons TLB Benefits? Scheduling? Invalidating?

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