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Fig. 4 Large-area solution-processed CdSe TFT arrays on a Si wafer and on glass substrates. Large-area solution-processed CdSe TFT arrays on a Si wafer.

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Presentation on theme: "Fig. 4 Large-area solution-processed CdSe TFT arrays on a Si wafer and on glass substrates. Large-area solution-processed CdSe TFT arrays on a Si wafer."— Presentation transcript:

1 Fig. 4 Large-area solution-processed CdSe TFT arrays on a Si wafer and on glass substrates.
Large-area solution-processed CdSe TFT arrays on a Si wafer and on glass substrates. (A) Photograph, optical microscope images, and schematics of CdSe TFTs fabricated on 2.5-inch glass substrates and a 4-inch Si wafer. (B) A series of TFT transfer characteristics on a glass substrate measured at each numbered segment (W/L = 200 μm/20 μm). (C) Transfer curves, photosensitivity, and dynamic ranges of CdSe phototransistors under pulsed-laser wavelengths of 406 nm (blue), 520 nm (green), and 638 nm (red). (D) Oscillation frequency and propagation delay per stage as a function of supply bias (VDD) for a seven-stage CdSe ring oscillator circuit. (E) Threshold voltage shift (ΔVT) of CdSe TFTs under positive gate bias stress measured in air and N2 ambient. Sung Min Kwon et al. Sci Adv 2018;4:eaap9104 Copyright © 2018 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works. Distributed under a Creative Commons Attribution NonCommercial License 4.0 (CC BY-NC).

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