1. 332:437 Lecture 14 Turing Machines and State Machine Sequences
Iterative logic networks
State machine properties
Distinguishing and Homing sequences
State machine design to minimize hardware
Summary
Material from Switching and Finite Automata Theory, by Zvi Kohavi, McGraw-Hill Book Company.
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Bushnell: Digital Systems Design Lecture 14

2. Turing and State Machines
Called non-writing machines
Have no control on their external input
Cannot “write” or change their inputs
Turing Machine – after A. M. Turing
A writing machine
Finite State Machine capable of modifying its own input symbols
Fundamental Theoretical Model of all digital computers
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Bushnell: Digital Systems Design Lecture 14

3. Bushnell: Digital Systems Design Lecture 14
Turing Machine
Tape divided into squares – each contains a symbol (blank squares store a 0)
Head has 3 operations:
Read symbol in square being scanned
Write new symbol in scanned square
Shift tape 1 square in either direction
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Bushnell: Digital Systems Design Lecture 14

4. Turing Machine (cont’d.)1
Tape
Finite-State
Control Unit
Head
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Bushnell: Digital Systems Design Lecture 14

5. Bushnell: Digital Systems Design Lecture 14
Cycle of Computation
Start in state Si
Read symbol under head
Write new symbol
Shift left/right
Enter new state Sj
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Bushnell: Digital Systems Design Lecture 14

6. Turing Machine Example
Present State A
B C D Halt --
C, 1, R
D, 0, L
A, 0, R
Halt 1
B, 0, R
B, 1, R
D, 1, L
Next State, Write, Shift 1 ^A ^C
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Bushnell: Digital Systems Design Lecture 14

7. Turing Machine Properties
Anything a Universal Turing Machine can do, a digital computer can do
Anything a Universal Turing Machine cannot do, a digital computer cannot do
Emulation – A Universal Turing Machine can mimic or emulate the behavior of any other Turing Machine (and therefore, so can a computer)
Halting Problem – A Universal Turing Machine (and therefore a computer) cannot predict when the computation of another Turing Machine will complete, and when it will not
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Bushnell: Digital Systems Design Lecture 14

8. Iterative Logic Network
Digital structure having cascade of identical cells
Each may be a sequential circuit
Every finite output sequence that can be produced sequentially by a sequential machine can be produced spatially (or simultaneously) by a combinational iterative network
Cell Table – like State Machine transition table PS A B C D
xi = 0
B/0
D/0
xi=1
A/0
C/0
C/1
NS, Zi
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Bushnell: Digital Systems Design Lecture 14

9. Example Iterative Logic Array
l inputs
m outputs
k state variables
i time frames
x21
x22
x2l
xi1
xil
x11
x12
x1l
z11
z12
z1m
z21
z22
z2m
zi1
zi2
zim
Y21
Y2k
Yi1
Yik
yi1
yik
Cell 1
Cell 2
Cell 3
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Bushnell: Digital Systems Design Lecture 14

10. Iterative Logic Arrays
If same assignment used for iterative network as for sequential circuit
Logic of cell & combinational logic of sequential circuit are identical
# cells in iterative network must equal length of input patterns
Iterative network is a time-unraveled history of the inputs to the state machine
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Bushnell: Digital Systems Design Lecture 14

11. Formal Definition of Finite State Machine
State Transition Function:
S (t + 1) = d {S (t), x (t) }
Output Function:
z (t) = l {S (t), x (t) }
Synchronous Sequential Machine – quintuple:
M (I, O, S, d, l)
d: I X S S
l: I X S O
S O
I, O, S: Sets of inputs, outputs, & states
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Bushnell: Digital Systems Design Lecture 14

12. Synchronous Sequential Machines
View machine’s computation as transformation of input sequence into output sequence
If input sequence X takes machine from state Si to State Sj, then Sj is the X-successor of Si
If no input sequence exists to take machine M out of state D, then D is called a terminal state if:
Corresponding vertex in state transition diagram is a sink vertex
Corresponding vertex – no arcs coming from other vertices terminate at this one (source) –- Not accessible from any other state
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Bushnell: Digital Systems Design Lecture 14

13. State Machine Properties
Example
Give an n-state machine an arbitrarily long sequence of 1’s.
Sequence is longer than n, so machine must arrive at some state it was already in before
Period of machine – time between repetition of states
Cannot be > n, could be smaller
Conclusions:
Finite State Machines cannot recognize infinite, aperiodic sequences of inputs
Arbitrary Precision Serial Multiplication – not solvable by fixed FSM (fixed # of states)
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Bushnell: Digital Systems Design Lecture 14

14. Distinguishing Sequences
Finite input sequence that, when applied to FSM M, causes different output sequences
Depending on whether Si or Sj was the starting state
Called the Distinguishing Sequence of state pair (Si, Sj)
If the sequence is of length K, then (Si, Sj) states are K-distinguishable
States not K-distinguishable are K-equivalent
If, for all K, states are K-equivalent, then the states are simply equivalent
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Bushnell: Digital Systems Design Lecture 14

15. Bushnell: Digital Systems Design Lecture 14
Homing Sequences
Input sequence is a Homing Sequence if final state of the machine can be uniquely determined from machine’s response to the sequence
Regardless of the initial state
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Bushnell: Digital Systems Design Lecture 14

16. State Assignments to Minimize Hardware
Done to minimize next state decoder hardware
Rule 1: States having same NEXT STATES for a given input condition should have logically adjacent map cells
Logical Adjacency
100
101
110
111
000
1/-
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Bushnell: Digital Systems Design Lecture 14

17. State Assignments to Minimize Hardware
Rule 2: States that are NEXT STATES of a single state should have assignments that can be grouped into logically adjacent MAP cells
Corollary: Make the assignments correspond to the branching (input) variable(s) – Reduced Input Dependency
100
101
110
111
000
11/
10/
01/
00/
Should be the same
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18. Bushnell: Digital Systems Design Lecture 14
Summary
Turing Machines
Iterative logic networks
State machine properties
Distinguishing and Homing sequences
State machine design to minimize hardware
11/5/2019
Bushnell: Digital Systems Design Lecture 14