1. Pixel Digital Simplification
Wei Wei

2. Outline Pixel digital/encoder simplification
Tried 4 schemes
Some issues of the address buffer
Design proposal
并行设计较多，仿真比较仓促，请随时指正！

3. To simplify the pixel digital/address design
Motivation: reduce the duplicated logic in pixel digital and encoder
Priority logic existed in both pixel digital and encoder, keep one
Any possibility to reduce the complexity of the encoder layout?
Scheme 1：
Keep the encoder unchanged, simplify the pixel digital
Proposed in the last meeting by Xiaomin
Tried other two schemes
Scheme 2：
Keep the pixel digital, simplify the encoder
Scheme 3：
To simplify the encoder furthermore, based on scheme 2

4. Scheme 1: less digital, same encoder
Keep encoder unchanged
Delete fastor, priority, read token logic in pixel digital; keep hit gen, hit reset (proposed edge detection not involved, but can be added)
Sim: use real analog, real encoder( 4bit), ideal periphery. Bus RC load were included
Func works

5. Scheme 2a：same digital, less encoder
Keep digital unchanged
Delete the sync reset logic, the priority logic were simplified to inverters. They are included in the pixel digital
The real encoder keep unchanged
Sim: same as previous
Func works
Simplify to inv
same

6. Scheme 2b：to ease the layout complexity
Based on scheme 2a
In layout, 2a will have some inter-pixel connections due to the group of encoder
The lower rows have to deal with many cross-connection buses
Try to ease the layout complexity further
Separate the encoder to independent bit-> every pixel now only face its own bits
Actually based on tristate buffers
Func works
Simulation results omitted
Disadvantages:
Every pixel has to layout all the 9bits for 512 row address
It looks very much like the pull up scheme
Pixel addr=2’b10

7. Scheme 2c: further easy the layout complexity
Based on scheme 2b
To simplify every bit logic into one transistor
Easier layout
Although every pixel still has to place all the 9bits, every bit has only one transistor
13 transistors shared by 4 pixels (lower group level), but has to leave space for higher level transistors
there is no inter-pixel connection now, only global addr buses
Intrinsic pullup connection, not high-Z bus anymore
Func works (same sim. condition)
Questions:
Power consumption is big as mentioned?

8. Comparison of the candidate schemes
Not consider sch 2b anymore
Power consumption depends on basic blocks, but also bus buffers and bus RC load
Scheme 2c don’t need buffers, whereas scheme 1 & 2a need buffers
To evaluate power and delay (TDA), under the same condition
Read given after 8 segs of buffer+RC load
Buffer from std cell lib: buffd1
Encoder output with 8 segs of buffer+RC load
Buffer designed by Tianya: wire_buffer
Pullup scheme output with 8segs of RC_only
Terminated with bufbd1
460ohm
400f X8 X8
read X8
read

9. Power consumption Sch 1 Sch 2a Sch 2c
Total current of the encoder was checked, some issues:
Sch 1 &2a: due to high Z state at the initial state, the input of the wire buffer will suffer from large current after first readout, the current becomes normal (nA~pA)
The average current was used to judge the power consumption:
200ns~600ns, tt:
200ns~2us,
200ns~600ns, ss, 50:
200ns~8u, ss, 50:
When used std_cell tristate buffer, the trend were the same
That means: sch 2c is not really more power consuming, because it doesn’t need buffer

10. Timing performance:delay@TDA
TDA: read from periphery -> addr arrive at periphery was used to evaluate the timing performance
Buffer and RC load were included, but encoder only used the 4-bit block, with the rest 8 seg buffers
@tt:
@ss, 50:
This means: sch1 is the fastest as expected, but all the 3 sch are at the same level

11. Combined comparison Note: Conclusion & proposal
Sch 1 (less digital, same enc)
Sch 2a (same digital, less enc)
Sch 2c (same digital, + pull up)
Power
same
Same
~ ½ lower
Timing
1st (16.03ns)
2nd (16.91ns)
3rd (17.89ns)
Area
Med
Layout complexity
Easy
Possible risk
High Z, wire buffer
-- (?)
Advantage
Keep most of design from MOST1
Proved performance from ATLAS 25ns BX, with ALPIDE encoder
Easier layout; may save the power from buffers
Note:
For the encoder scheme (1 &2a), not all the rest logics and groups were included, will add some more power and delay
The power consumption due to the high Z + wire buffer seems to be a potential issue, need to be further verified by Tianya
Conclusion & proposal
Sch 1，2a, & 2c all seemed to be effective simplifications from the original design
Maybe we should try parallel designs in this tapeout

12. Preliminary consideration of the schedule
From MOST2 project
05/2018 ~ 04/2019 the first MPW to be tapeout