1. Advanced Computer Architecture Lecture 23
Tree and hypercube interconnects
Routers
Lillevik s06-l23
University of Portland School of Engineering

2. No global or shared memory
Distributed computer
Interconnect P M
...
No global or shared memory
Lillevik s06-l23
University of Portland School of Engineering

3. Trees may have k nodes-per-branch
Binary tree
Binary tree: re-drawn
Trees may have k nodes-per-branch
Lillevik s06-l23
University of Portland School of Engineering

4. Find the following? Diameter: 2log2n Average distance: log2n
Binary tree, n nodes
Diameter: 2log2n
Average distance: log2n
Bisection BW: 1
Lillevik s06-l23
University of Portland School of Engineering

5. Cables problematic for large D
Hypercube
4-D
2-D
0-D
1-D
3-D
5-D
Cables problematic for large D
Lillevik s06-l23
University of Portland School of Engineering

6. Hypercube, n nodes (n = 2D)
Find the following?
Hypercube, n nodes (n = 2D)
Diameter: log2 n
Average distance: log2 n
Bisection BW:
Lillevik s06-l23
University of Portland School of Engineering

7. Routing algorithms Route: path a message must traverse
Node ID = (x, y, z, …)
Algorithm
Route x dimension, then y, etc.  in order
Avoids deadlock, maximum utilization
Lillevik s06-l23
University of Portland School of Engineering

8. Node (1,0) sends message to node (2,3)
Mesh routing example
(0,0)
(3,0)
(3,3)
(0,3)
Node (1,0) sends message to node (2,3)
(1,0)  (2,0)  (2,1)  (2,2)  (2,3)
x - dim
y - dim
Lillevik s06-l23
University of Portland School of Engineering

9. Node (1,0,0) sends message to node (0,1,1)
Find routing path?
(0,0,0)
(1,0,0)
(1,1,0)
(0,1,1)
(1,1,1)
(0,0,1)
Node (1,0,0) sends message to node (0,1,1)
Lillevik s06-l23
University of Portland School of Engineering

10. Nodes connected by links
Processor
and
Router
link
Node
Processor
Router
Links
Simple bus
Protocol
Lillevik s06-l23
University of Portland School of Engineering

11. Router connects processor to links
Router interfaces
Router 
Processor
Interface
Link
Interfaces
Router connects processor to links
Lillevik s06-l23
University of Portland School of Engineering

12. Processor interface signals?
A, D, C buses
Ack, clk, reset
Breq, BGnt
Ben
Lillevik s06-l23
University of Portland School of Engineering

13. Link interface signals?
Send, receive
IRQ, INTA
Ready
Lillevik s06-l23
University of Portland School of Engineering

14. Unidirectional ring router
Processor
Ring router contains three ports
Lillevik s06-l23
University of Portland School of Engineering

15. Unidirectional ring router signals
IReq
IAck In
OReq
OAck
Out
RReq
WReq
RAck
WAck D
Link input
Link output
Processor
Lillevik s06-l23
University of Portland School of Engineering

16. Mesh router contains five ports
North
Router
West
East
South
Processor
Mesh router contains five ports
Lillevik s06-l23
University of Portland School of Engineering

17. Mesh router signals? ERReq, ERAck, ….. Lillevik 437s06-l23
University of Portland School of Engineering

18. Ring router block diagram
In I/F
Out I/F
CPU I/F
Latch
Controller
Driver
Lillevik s06-l23
University of Portland School of Engineering

19. Ring router schematic Lillevik 437s06-l23
University of Portland School of Engineering

20. Ring router modes Pass Write: CPU writing to router (source)
Message passing through router, independent of local CPU activity
Source an upstream CPU, destination a downstream CPU
Write: CPU writing to router (source)
Read: CPU reading from router (destination)
DMA
Lillevik s06-l23
University of Portland School of Engineering

21. Interference
Routers support multiple modes (pass, read, write, broadcast, etc.)
Some modes independent and support concurrency (parallel)
Some modes are exclusive (dependent)
Requires arbitration to resolve
Results in message blocking and network interference
Lillevik s06-l23
University of Portland School of Engineering

22. Pass mode data flow Latch In Out In I/F Controller Out I/F CPU I/F
Driver
Lillevik s06-l23
University of Portland School of Engineering

23. Write mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F
Driver
Lillevik s06-l23
University of Portland School of Engineering

24. Read mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F
Driver
Lillevik s06-l23
University of Portland School of Engineering

25. Message format Header: routing and control information Payload: data
Trailer: error checking code (ECC)
time
Trailer
Payload
Header
Lillevik s06-l23
University of Portland School of Engineering

26. Eight-node example 4 6 1 3 7 5 2 Write Pass Read Lillevik 437s06-l234 6 1 3 7 5 2
Write
Pass
Read
Lillevik s06-l23
University of Portland School of Engineering

27. Lillevik s06-l23
University of Portland School of Engineering

28. Find the following? Diameter: 2 log2 n Average distance: log2 n
Binary tree, n nodes
Diameter: 2 log2 n
Average distance: log2 n
Bisection BW: 1
Lillevik s06-l23
University of Portland School of Engineering

29. Hypercube, n nodes (n = 2D)
Find the following?
Hypercube, n nodes (n = 2D)
Diameter: log2 n
Average distance: 1/2 log2 n
Bisection BW:
Lillevik s06-l23
University of Portland School of Engineering

30. Node (1,0,0) sends message to node (0,1,1)
Find routing path?
(0,0,0)
(1,0,0)
(1,1,0)
(0,1,1)
(1,1,1)
(0,0,1)
Node (1,0,0) sends message to node (0,1,1)
(1,0,0)  (0,0,0)  (0,1,0)  (0,1,1)
Lillevik s06-l23
University of Portland School of Engineering

31. Processor interface signals?
Processor output request
Processor output acknowledge
Processor input request
Processor input acknowledge
Lillevik s06-l23
University of Portland School of Engineering

32. Link interface signals?
Link output request
Link output acknowledge
Link input request
Link input acknowledge
Lillevik s06-l23
University of Portland School of Engineering

33. Mesh router signals? PIReq, PIAck, POReq, POAck, PData
NIReq, NIAck, NOReq, NOAck, NData
EIReq, EIAck, EOReq, EOAck, EData
SIReq, SIAck, SOReq, SOAck, SData
WIReq, WIAck, WOReq, WOAck, WData
Lillevik s06-l23
University of Portland School of Engineering

34. Write mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F
Driver
Lillevik s06-l23
University of Portland School of Engineering

35. Read mode data flow? Latch In Out In I/F Controller Out I/F CPU I/F
Driver
Lillevik s06-l23
University of Portland School of Engineering