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Advanced Computer Architecture Lecture 3
CPU model Controller design Lillevik s06-l3 University of Portland School of Engineering
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Bus: collection of n parallel signals
What is a bus? ··· Agent 0 Agent n ··· Signal 0 Signal n Bus Bus: collection of n parallel signals Lillevik s06-l3 University of Portland School of Engineering
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CPU functional diagram
Model Reset/ Clk Ack Busgnt Int C A D Busreq Inta Lillevik s06-l3 University of Portland School of Engineering
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Inputs Reset/ Places CPU in known state
Clk Clock for synchronous logic Ack Indicates bus cycle complete Busgnt Bus granted to CPU Int Interrupt request Lillevik s06-l3 University of Portland School of Engineering
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Outputs A Address of bus operation (8 bits)
D Data for bus operation, it is a bi-directional bus (8 bits) C Control bits indicate type of bus operation (4 bits) Busreq CPU requests use of bus Inta CPU acknowledges an interrupt input Lillevik s06-l3 University of Portland School of Engineering
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Note: no data read into CPU
CPU block diagram PC ROM FSM Tri-State Buffer Breq Inta Bgnt Ack Int C A D Note: no data read into CPU Lillevik s06-l3 University of Portland School of Engineering
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CPU schematic Instruction Project 2 Lillevik 437s06-l3
University of Portland School of Engineering
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Instruction format Data Address Control 7 8 F 10 13 N/A 14 31 4-bits
7 8 F 10 13 N/A 14 31 4-bits 8-bits 8-bits I/O Write 1 No operation I/O Read Mem Write Mem Read Function C0 (read) C1 (write) C2 (memory) C3 (I/O) Data bus driven Lillevik s06-l3 University of Portland School of Engineering
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Programming the model Create a text file for ROM256x32
All execution starts at PC = 0 User must specify Control, Address, and Data fields Update links and execute B2Logic simulator Lillevik s06-l3 University of Portland School of Engineering
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Find the instruction? Memory read at address 0xf4
I/O write 0x55 to port 0xa Lillevik s06-l3 University of Portland School of Engineering
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One CPU, memory agent, I/O agent
System Example CPU Memory I/O Pull Ups Clock Reset/ Bus One CPU, memory agent, I/O agent Lillevik s06-l3 University of Portland School of Engineering
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Timing Signal Agent Data Bus Driven Clk Breq Bgnt Ack Arb CPU/Master
Adr Arbiter Slave Ack Lillevik s06-l3 University of Portland School of Engineering
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Controller design One section of CPU model Finite state machine
Synchronous Inputs Outputs Present state Next state Lillevik s06-l3 University of Portland School of Engineering
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FSM design Assume: sequential solution
Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik s06-l3 University of Portland School of Engineering
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CPU requirements Reset state (asynchronous) Respond to nop instruction
Request use of bus Wait until it owns the bus Drive the bus (A, D, C) Wait until bus agent is ready Respond to an interrupt Get next instruction Lillevik s06-l3 University of Portland School of Engineering
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Nop instruction Purpose: to waste time, but not stop CPU Application
Used to wait until an interrupt occurs DMA bus agent signals completion with Int Implementation Check to see if instruction is a nop Insert some wait states in controller Do not drive the bus Lillevik s06-l3 University of Portland School of Engineering
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Interrupt Purpose: to allow a bus agent to “wake up” CPU
Application: DMA bus agent signals completion with Int Implementation Check if Int asserted at end of each bus cycle Response: stop CPU NOTE: interrupts always enabled Lillevik s06-l3 University of Portland School of Engineering
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Internal signals Definition: signal used by the CPU model that does not appear on the bus Implementation: CPU controller signals Nop input indicates that instruction is a nop Count output increments the PC Ben output enables tri-state drivers Lillevik s06-l3 University of Portland School of Engineering
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Find the signals? Requirement Signals Reset state
Respond to nop instruction Nop Request use of bus Breq Wait until it owns the bus Bgnt Drive the bus (A, D, C) Ben Wait until bus agent is ready Ack Respond to an interrupt Inta Get next instruction Count Lillevik s06-l3 University of Portland School of Engineering
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FSM design Assume: sequential solution
Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options Lillevik s06-l3 University of Portland School of Engineering
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Partial state diagram Skip over: nop, interrupt, count Focus on bus
Request use of bus Wait until it owns the bus Drive the bus (A, D, C) Wait until bus agent is ready Get next instruction Lillevik s06-l3 University of Portland School of Engineering
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Timing Signal Agent Data Bus Driven Clk Breq Bgnt Ack Arb CPU/Master
Adr Arbiter Slave Ack Lillevik s06-l3 University of Portland School of Engineering
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Find partial state diagram?
c f a Reset Inputs, Outputs Lillevik s06-l3 University of Portland School of Engineering
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Full state diagram Nop Interupt Count: assert at end of loop
Check right after reset Add same number of states as a bus cycle Interupt Check at end of bus cycle Enter state with no exit (stop) Count: assert at end of loop Lillevik s06-l3 University of Portland School of Engineering
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Find full state diagram?
b a c d f g h e i l j k Inputs, Outputs Lillevik s06-l3 University of Portland School of Engineering
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Lillevik s06-l3 University of Portland School of Engineering
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Find the instruction? Memory read at address 0xf4
I/O write 0x55 to port 0xa 0x a 0a 55 Lillevik s06-l3 University of Portland School of Engineering
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Find the signals? Requirement Signals Reset state Reset/
Respond to nop instruction Nop Request use of bus Breq Wait until it owns the bus Bgnt Drive the bus (A, D, C) Ben Wait until bus agent is ready Ack Respond to an interrupt Int, Inta Get next instruction Count Lillevik s06-l3 University of Portland School of Engineering
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Find partial state diagram?
Bgnt Bgnt d e Ack Breq Breq, Ben Ack Breq c f Reset Breq, Ben a Reset Lillevik s06-l3 University of Portland School of Engineering
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Find full state diagram?
b a c d f g h e i l j k Reset nop Bgnt Ack Breq Breq, Ben Int Inta Count Lillevik s06-l3 University of Portland School of Engineering
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