1. Lecture 1: Introduction

2. Courtesy Texas Instruments
A Brief History
1958: First integrated circuit
Flip-flop using two transistors
Built by Jack Kilby at Texas Instruments
2010
Intel Core i7 mprocessor
2.3 billion transistors
64 Gb Flash memory
> 16 billion transistors
Courtesy Texas Instruments
[Trinh09]
© 2009 IEEE
1: Circuits & Layout

3. Growth Rate 53% compound annual growth rate over 50 years
No other technology has grown so fast so long
Driven by miniaturization of transistors
Smaller is cheaper, faster, lower in power!
Revolutionary effects on society
[Moore65]
Electronics Magazine
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4. Annual Sales >1019 transistors manufactured in 2008
1 billion for every human on the planet
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5. MOS Integrated Circuits
1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
Intel Museum.
Reprinted with permission.
[Vadasz69]
© 1969 IEEE.
Intel bit SRAM
Intel bit mProc
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6. Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale
Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: gates
LSI: 10,000 gates
VLSI: > 10k gates
[Moore65]
Electronics Magazine
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7. And Now…
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8. Feature Size Minimum feature size shrinking 30% every 2-3 years
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9. Corollaries Many other factors grow exponentially
Ex: clock frequency, processor performance
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10. Introduction Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
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11. Silicon Lattice Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
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12. Dopants Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
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13. p-n Junctions
A junction between p-type and n-type semiconductor forms a diode.
Current flows only in one direction
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14. nMOS Transistor Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal – oxide – semiconductor (MOS) capacitor
Even though gate is
no longer made of metal*
* Metal gates are returning today!
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15. nMOS Operation Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
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16. nMOS Operation Cont. When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from source through channel to drain, transistor is ON
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17. pMOS Transistor Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
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18. Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
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19. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain
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20. CMOS Inverter A Y 1
OFF ON 1 ON
OFF
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21. CMOS NAND Gate A B Y 1 OFF ON 1 OFF ON 1 ON OFF ON OFF 11
OFF ON 1
OFF ON 1 ON
OFF ON
OFF 1
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22. CMOS NOR Gate A B Y 1
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23. 3-input NAND Gate Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
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24. Compound Gate
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25. Fig. 13. 16 Proper transistor sizing for a four-input NOR gate
Fig Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) rations of QN and QP, respectively, of the basic inverter.
Microelectronic Circuits - Fourth Edition Sedra/Smith

26. Fig. 13. 17 Proper transistor sizing for a four-input NAND gate
Fig Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) rations of QN and QP, respectively, of the basic inverter.
Microelectronic Circuits - Fourth Edition Sedra/Smith

27. Non-inverting Buffer

28. AND Gate

29. OR Gate

30. Inverter+NAND+NOR

31. Inverter+NAND+NOR
Design a CMOS digital circuit that realizes the Boolean function

32. CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or etched
Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process
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33. Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
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34. Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
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35. Inverter Mask Set Transistors and wires are defined by masks
Cross-section taken along dashed line
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36. Detailed Mask Views Six masks n-well Polysilicon n+ diffusion
p+ diffusion
Contact
Metal
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37. Fabrication Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
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38. Fabrication Steps Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
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39. Oxidation Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
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40. Photoresist Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
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41. Lithography Expose photoresist through n-well mask
Strip off exposed photoresist
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42. Etch Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
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43. Strip Photoresist Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
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44. n-well n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
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45. Strip Oxide Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
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46. Polysilicon Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
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47. Polysilicon Patterning
Use same lithography process to pattern polysilicon
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48. Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well contact
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49. N-diffusion Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing
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50. N-diffusion cont. Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
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51. N-diffusion cont. Strip off oxide to complete patterning step
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52. P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
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53. Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
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54. Metalization Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
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55. Layout Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
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56. Simplified Design Rules
Conservative rules to get you started
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57. Inverter Layout Transistor dimensions specified as Width / Length
Minimum size is 4l / 2l, sometimes called 1 unit
In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
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58. Pass Transistors Transistors can be used as switches
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59. Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
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60. Tristates Tristate buffer produces Z when not enabled EN A Y Z 1Z 1
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61. Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
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62. Tristate Inverter Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
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63. Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1X 1
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64. Gate-Level Mux Design How many transistors are needed? 20
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65. Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors
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66. Inverting Mux Inverting multiplexer Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
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67. Inverting Mux
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68. 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
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69. D Latch When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
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70. D Latch Design
Multiplexer chooses D or old Q
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71. D Latch Operation
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72. D Flip-flop When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave flip-flop
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73. D Flip-flop Design Built from master and slave D latches
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74. D Flip-flop Operation
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75. Race Condition Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
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76. Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
Industry manages skew more carefully instead
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77. Gate Layout Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
VDD and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
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78. Example: Inverter
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79. Example: NAND3 Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
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80. Stick Diagrams Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
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81. Wiring Tracks A wiring track is the space required for a wire
4 l width, 4 l spacing from neighbor = 8 l pitch
Transistors also consume one wiring track
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82. Well spacing Wells must surround transistors by 6 l
Implies 12 l between opposite transistor flavors
Leaves room for one wire track
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83. Area Estimation Estimate area by counting wiring tracks
Multiply by 8 to express in l
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84. Example: O3AI Sketch a stick diagram for O3AI and estimate area
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85. Summary MOS transistors are stacks of gate, oxide, silicon
Act as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start designing schematics and layout for a simple chip!
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86. About these Notes Lecture notes © 2011 David Money Harris
These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.
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