1. Phase Frequency Detector &
Front-end Digitization for fast Imagers.
Pradeep Kalavakuru, Inge Diehl
Matter and Technologies
Detector Development
Key Design Blocks for Pixel Detectors
DEPFET Sensor with Signal Compression (DSSC)
Digital Silicon Photomultiplier
Front-end
Counter
Serializer
V/I
References
Pixel
TDC S
Particle Tracking and Imaging
Hit Matrix & Time Stamp
Active Quenching and Recharging
Continuous Operation
Sensor
Data out
Single Photon Counting
Intensity Matrix
Low Noise
Pulsed Operation
Pixel
Front-end
ADC
MEMORY
Serializer
V/I
References
Counter
Sensor
Data out
Advantage of Front-end Digitization
Best Signal-to-Noise Ratio
High Flexibility for Technology Scaling
→ Our Approach: In-Pixel Digitization
Analog
Digital
Design
Single-slope ADC
Pixel
ASIC
236 µm
15 mm
Pixel
TDC
50 µm
160 µm
ASIC
1.9 mm
MEMORY
105 µm
55 µm
57 µm
4096 Pixels
2.1 mm
Receivers
14 mm
204 µm FE +
Control-Logic
Offset
Trimming
120 µm
Comparator
TRG
32 element delay line Vcontrol
DLL
Ripple Counter
5 bit
7 bit
Latch
Encoder
Phase Frequency Detector &
Current Pump D C Q _
Gain Trimming
Hold Time
Hit Counter
2 bit
Anode
Quench
Recharge
Serializer
AQRC
Vqt
Vrt
Trigger
3.3 V
1.2 V
V / I Reference
64 x Tx & GCC
CLK
In Pixel
Ping-Pong Buffering
Ramp Generation with Gain Trimming (6 bit)
Delay for Offset Trimming (4 bit)
Differential Latches
Global
8-bit Gray-Code Counter
Time-Stamps distributed over coplanar Wave Guides
Features
Sampling Rate: 4.5 MS/s (typ.), 10 MS/s (max.)
Dynamic Range: 1V
Resolution: 8 bit
GCC-Bin Width: 720 ps (typ.), 300 ps (min.)
Noise: 180 µVrms
Temp. Stability: ±1% of Gain from -40°C - 40°C
Core Area: mm2
Operating Region:
Core Voltage: 1.1 V…1.4 V, 1.3 V (typ.)
Temperature: -40°C…50°C, -20°C (typ.)
Peak Power Dissipation:
530 µW (Analog)
288 µW (Digital)
*ASIC Team: University of Heidelberg, Politecnico di Milano, Universita di Bergamo, DESY
Full-Matrix Readout Chip*
64 x 64 Pixels
GF 130 nm CMOS, C4 Bumps
Serial Data 350 Mbps
Slow Control (JTAG)
Power Dissipation (Power 10 Hz)
→ < 100mW per ASIC
In Pixel
Digital Front-end with active Quenching and Recharging
Wired-OR Trigger
Hit Counting
Adjustable Start/Hold-Time of Recharge Signal for Reducing pile-up Effects
Global
Delay Lock Loop as fine TDC
Ripple Counter as coarse TDC
32-to-5 bit Encoder
Hit Validation via Thresholds (4 per Row, 2 per Matrix)
Gain → 320 LSB / V
Features
Pixel Matrix: 16 x 16
Process: GF 130 nm CMOS, SAC Bumps
Frame Rate: 3 MHz
Throughput: 1 Gbps (typ.), 1.6 Gbps (max.)
Trigger Delay: <2 ns
TDC Resolution: 12 bit
TDC-Bin Width: 77 ps
Core Area: mm² (Pixel)
mm² (TDC)
Core Voltages: 1.2 V and 3.3 V
Power Dissipation: 140 mW → 550 µW/Pixel
(I/O: 110 mW, Core: 30 mW)
Anode
Quench
Recharge
Quenching Time ns
Recharging Time ns
Vth ≈ 1 V
σ = 0.16 adu
Results
Lab-Test Condition
Power Cycling ( Hz, Room Temperature)
On-Chip DAC (13 bit, 100 µV step)
Lab-Test Condition
Pixel Enabling
Global Test Input
Separate TDC
3-MHz Frame Rate
Gain ( LSB / V)
INL (ADU)
DNL (ADU)
Automated Gain Trimming
Trimming reduces Spread to ± 2%
σmean = 0.4 LSB
No missing Bins
σmean = 0.18 LSB
Propagation Delay from Pixel Input to Triggering the TDC of 2 Chip Samples
Dependent of enabled Pixel
Bin Width: µ = ps, σ = ps
DNL: σ = 0.15 LSB
INL: σ = 0.33 LSB
Petra III (P65 Beam Line)
Beam focused onto a 8 µm thick Cu foil (Fluorescense)
Center of Energy for Cu-Kα /Kβ → keV
Frame Rate → 2.6 MHz
Connected to Sensor Matrix
cps
Room Temperature
Mean Count Rate
→ 230 kcts/s/pixel
Counts
Mean-Noise → ~ 80 e-
Noise (e-)
Mean Sensitivity → 0.72 keV/Bin
Mean Noise peak → 41.86
Mean Signal peak → 50.03
Sensitivity → 1 keV / Bin
ENC → ~80 e-
8.17 40 50 60 70 80
ADU
103
101
102
104
105 10
Counts
Vbd ≈ 35 V (Breakdown)
Vbias = Vbd + Vov (Overvoltage)
Threshold of Front-end Inverter ≈ 1 V
dSiMPl Sensor from MPG-HLL
Dark-Count Rate of individual Pixel
Noisy Pixel could be disabled