1. AVR UART
The UART, or Universal Asynchronous Receiver Transmitter, provides hardware support for a serial port on AVR processors
Signaling is compatible with PC/Mac/Unix serial (RS-232C)
The UART provides:
Parallel-to-Serial and Serial-to-Parallel conversion
Start and Stop Bit framing
Parity Generation
Baud-Rate Generation ( kbps at or 7.37MHz)
Interrupts
Transmit Complete
Transmit Data Register Empty
Receive Complete

2. Data Voltages Start bit 6,7,8,9 data bits
Parity bit optional (E,O,M,S,N)
Stop bit
Voltages
Processor outputs 0/5V logic-level signal
RS-232C uses +12V/-12V signal
Level-converter IC provided on STK500 (MAX202)

3. Serial frame format:
Every frame will have at least
-one start bit
-some data bits (5,6,7,8 or 9)
-one stop bit
Parity is optional

4. - The USART internal clock is set by the UBRR register.
The internal clock is derived from the internal
CPU clock.
Both transmitter and receiver use the same clock to
operate from. The transmitter is synchronous to the
clock. In coming data to the receiver is not.
The baud rates are not exact power of 2 multiples
of the CPU clock, thus baud rate inaccuracies
occur at some settings.

5. UART REGISTERS UDR (UART Data Register) USR (UART Status Register)
Write bytes to transmit
Read received bytes
USR (UART Status Register)
Rx/Tx complete signal bits
Framing error, overflow signal bits
UCR (UART Control Register)
Interrupt enable bits
Rx/Tx enable bits
Data format control bits
UBRR (UART Baud Rate Register)
Baud rate generator division ratio

6. UART BAUDRATE
It is set by UBRR
It varies with Fck.

7. Handshaking signals CTS- Clear to send RTS-Ready to send
DTR-Data terminal ready
DSR-Data set ready
DCD-Data carrier detect
RI-Ring indicator

8. C program For initialisation
Initialisation: void init_uart (unsigned long baudrate) { unsigned int ubrr = (F_CPU/16/baudrate)-1; // Set baud rate UBRRH = (unsigned char)(ubrr>>8); UBRRL = (unsigned char)(ubrr&0xff); // Enable receiver and transmitter UCSRB = ( 1<<TXEN | 1<<RXEN ); // select character size, stop and parity bits: 8N1 UCSRC = ( 1<<URSEL | 1<<UCSZ1 | 1<<UCSZ0 ); // enable receive complete interrupt UCSRB |= (1<<RXCIE); }

9. Data Transmission using UDRE Interrupt: (…) UCSRB |= ~(1<<UDRIE); (…) // enable UDRE-interrupts ISR (USART_UDRE_vect) // interrupt service routine UART Data Register empty { static int txindex=0; // transmit buffer index if (TXBuf[txindex]) // characters left ? UDR=TXBuf[txindex++]; // send current character from the buffer else { txindex=0; UCSRB &= ~(1<<UDRIE); } // Disable USART_UDRE interrupts, // reset character index }

10. Data Reception using RXC-Interrupt : ISR (USART_RXC_vect) // interrupt service routine USART character received { static int rxindex=0; // receive buffer index // read UDR and store received character RXBuf[rxindex++] = UDR; }