1. Fault Mitigation of Switching Lattices under the Stuck-At Model
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco and Elena Ioana Vatajelu
This project has received funding from the European Union's H research and innovation programme under the Marie Skłodowska-Curie grant agreement No

2. Outline Introduction Switching lattices and Logic Synthesis Method
Stack-At Faults in Lattices
Defect/Fault Tolerance
Conclusions

3. Introduction
Nano-crossbars are emerged as an alternative to CMOS technology
Cheap bottom-top nano-fabrication techniques
Fabrics yield to be regular and dense
Area and power efficient
Easy to implement Boolean functions: logic and arithmetic

4. Introduction Switching Nano-arrays Two-terminal switch
Four-terminal switch

5. Introduction Switching Nano-arrays Two-terminal switch
Diode based
Memristor based
Two-terminal switch
Switching nano array
Four-terminal switch
controlled by the voltage difference between the terminals.

6. Introduction Switching Nano-arrays Two-terminal switch
Diode based
Memristor based
Two-terminal switch
Switching nano array
FET based
Four-terminal
Four-terminal switch
FET based switch; here, the red line represents the controlling input. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays
A four-terminal switch is given The controlling input, has a separate physical formation from the crossbar

7. Introduction

8. Introduction
Nanowire four-terminal switch
Spin-wave switch

9. Introduction and Challenges
Memristive based crosspoint- the most promising
non volatility - > very usefull for memory intensive computing paradigms such as neuromorphic applications (prediction, classification, etc)
they can be programmed to store 2 states (binary) or multiple states (analog values)
Emerging technologies are quite immatures
permanent defects: hard faults – the resistance of the memristor will not change anymore – SA0 or SA1 faults
around 64% of memristive cells can be considered as fault free, 10% SA
instabilities, soft faults, variations – soft faults
- 10%

10. Introduction and Challenges
Need to understand the impact of defects and instabilities of memristive devices on logic function mapping algorithm
analyze the sensitivity of a decomposition algorithm face to SA0, and SA1
identify critical switches
propose mitigation methods to strengthen the mapping algorithm while keeping the crossbar area minimal

11. Outline Introduction Logic Synthesis Method
Stack-At Faults in Lattices
Defect/Fault Tolerance
Conclusions

12. Logic Synthesis Transient Fault Tolerance Logic Synthesis
Permanent Defect Tolerance
Testing Transient Fault Tolerance Performance
Transient Fault
Tolerance
Performance Optimization
Fabrication
Logic Synthesis

13. Introduction
𝑥 1 𝑥 2 𝑥 3 + 𝑥 1 𝑥 2 𝑥 5 𝑥 6 + 𝑥 2 𝑥 3 𝑥 4 𝑥 5 + 𝑥 4 𝑥 5 𝑥 6

14. Introduction
𝑥 1 𝑥 2 𝑥 3 + 𝑥 1 𝑥 2 𝑥 5 𝑥 6 + 𝑥 2 𝑥 3 𝑥 4 𝑥 5 + 𝑥 4 𝑥 5 𝑥 6

15. Introduction
𝑥 1 𝑥 2 𝑥 3 + 𝑥 1 𝑥 2 𝑥 5 𝑥 6 + 𝑥 2 𝑥 3 𝑥 4 𝑥 5 + 𝑥 4 𝑥 5 𝑥 6

16. Introduction
𝑥 1 𝑥 2 𝑥 3 + 𝑥 1 𝑥 2 𝑥 5 𝑥 6 + 𝑥 2 𝑥 3 𝑥 4 𝑥 5 + 𝑥 4 𝑥 5 𝑥 6

17. Introduction
𝑥 1 𝑥 2 𝑥 3 + 𝑥 1 𝑥 2 𝑥 5 𝑥 6 + 𝑥 2 𝑥 3 𝑥 4 𝑥 5 + 𝑥 4 𝑥 5 𝑥 6

18. Introduction The synthesis objective –
𝑥 1 𝑥 2 𝑥 3 + 𝑥 1 𝑥 2 𝑥 5 𝑥 6 + 𝑥 2 𝑥 3 𝑥 4 𝑥 5 + 𝑥 4 𝑥 5 𝑥 6
The synthesis objective –
finding assignements of literals to switches
for a given function
using lattice with minimal size

19. Logic Synthesis
Implementation of fXOR2 with different nanocrossbar types

20. Logic Synthesis Crossbar size limits (area) and Function size
Fabrication Complexity
Function output number (Multi or single output realization)
Power and Delay Specifications
Application specification (memory based etc.)

21. Outline Introduction Logic Synthesis Method
Stack-At Faults in Lattices
Sensitivity Analysis
Conclusions

22. Defect/Fault Tolerance
Permanent Defect Tolerance
Testing Transient Fault Tolerance Performance
Transient Fault
Tolerance
Performance Optimization
Fabrication
Logic Synthesis

23. Defect/Fault Tolerance
Permanent Faults occur mostly in fabrication and are tolerated in post-fabrication by redundancy and reconfigurability (mapping).
Transient Faults occur in field and are tolerated by redundancy

24. Sensitivity Analysis – SA0 and SA1
Proposed method utilizes a sensitivity analysis of crossbar to determine critical switches, and strengthens them with mitigation factors
fault injection platform – SA0 or SA1 injection in every cell, use uniform distribution
For each cross bar inputs, the simulation algorithm compares the given output with the correct one.
𝐸 𝑖𝑗 0 , 𝐸 𝑖𝑗 1 - the number of affected outputs when SA0 (resp., SA1)

25. Sensitivity Map
𝐸 𝑖𝑗 0
𝐸 𝑖𝑗 1
Lattice design
Sensitivity maps

26. Sensitivity Metrics Sensitivity metric: 𝑆 𝐿 0 = 𝐸 0 2 𝑛 𝑟×𝑠
The average n° of defective outputs on full lattice divided by the total number of inputs
𝑆 𝐿 0 = 𝐸 𝑛 𝑟×𝑠
𝑆 𝐿 1 = 𝐸 𝑛 𝑟×𝑠
𝑟×𝑠=𝑡ℎ𝑒 𝑎𝑟𝑒𝑎 𝑜𝑓 𝑡ℎ𝑒 𝑙𝑎𝑡𝑡𝑖𝑐𝑒, 𝐸 0 =# 𝑐𝑒𝑙𝑙𝑠 𝑟𝑜𝑏𝑢𝑠𝑡 𝑡𝑜 𝑆𝐴0, 2 𝑛 =𝑡𝑜𝑡𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑖𝑛𝑝𝑢𝑡𝑠

27. Sensitivity Evaluation
Realize a target logic function on a sensitive crossbar
row and column permutations (many synthesis algorithms exist)
SL0=1/12
SL1=1/24
SL0=1/9
SL1=1/18

28. Sensitivity Evaluation
To realize a target logic function on a sensitive crossbar
row and column permutations (many synthesis algorithms exist) – exponential number of possibilities
For the worst-case, N!M! permutations are required to find a successful mapping for NXM crossbar.
Defect-aware – considering defect characteristics (SA0 and SA1), then decide which switch to employ during the mapping
use combinations where two similar columns/rows are adjacent (contains at least one identical literal) – acts as a bypass in case of faults)
choose the literals that maximized the number of adjacent cells

29. Outline Introduction Logic Synthesis Method
Stack-At Faults in Lattices
Sensitivity Analysis
Conclusions

30. Synthesis and Sensitivity Results
Permute Rows
and Columns
LGSynth93 benchmark
initial Lattice
Permute Rows
Permute Columns
Choose Litterals

31. Outline Introduction Logic Synthesis Method
Stack-At Faults in Lattices
Sensitivity Analysis
Conclusions

32. Conclusions
Nano-switches are good alternatives to CMOS Boolean logic implementations
They are prone to defects and variability
Defect characterization and fault modeling are required for
Reliable computation (fault mitigation)
Area and power minimization under fault mitigation

33. Fault Mitigation of Switching Lattices under the Stuck-At Model
Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco and Elena Ioana Vatajelu
This project has received funding from the European Union's H research and innovation programme under the Marie Skłodowska-Curie grant agreement No