1. VHDL Synthesis for Implementing Digital Designs into FPGAs
MSc Cristian Sisterna
UNSJ

2. V H D L Very High Speed ICs Hardware Description Language Introduction
C. Sisterna
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3. Hardware Description Language
HDL
(VHDL/Verilog)
FPGA
ASIC
Xilinx
Altera
Lattice
Actel
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4. Hardware Description Language
High level of abstraction
Easy to debug
Parameterized designs
Re-uso
IP Cores (free) available
if(reset=‘1’) then
count <= 0;
elsif(rising_edge(clk)) then
count <= count+1;
end if;
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5. What is not VHDL
Verilog o VHDL IS NOT A programming language; IT IS A HARDWARE DESCRIPTION LENGUAGE
Verilog o VHDL is not (yet) a highly abstract language:
y(n) = 0.75y(n-1) + 0.3x(n) ;
(Simulink/FPGA design flow)
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6. HDL Synthesis Sub-Set VHDL VHDL Synthesizable
Used to write code to simulate the behavior of a design
VHDL
VHDL
Synthesizable
Used to implement the design into hardware (for instance in FPGA)
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7. VHDL ‘Description’ Examples
if(sel=‘1’) then
z <= y;
else
z <= x;
end if; z y 1
sel
z <= y when sel=‘1’ else x;
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8. VHDL ‘Description’ Ejemplos
if(clk )then
q <= d;
else
q <= q;
end if; q d
clk
if(clk )then
q <= d;
end if;
if(rising_edge(clk))then
q <= d;
end if;
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9. VHDL – Module Structure
ff.vhd
libraries& packages
entity q d
I/O
clk
architecture
functionality
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10. VHDL Module Structure q d clk ff.vhd entity ff is port(
library ieee;
useieee.std_logic_1164.all;
entity ff is
port(
d,clk : in std_logic;
q : out std_logic);
end ff;
entity f
port(
end ff;
architecture test of ff is
begin
process(clk)
end process;
end test;
architecture test of ff is
begin
process(clk)
if(rising_edge(clk)) then
q <= d;
end if;
end process;
end test; q d
clk
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11. VHDL Code – Is it really Works? ?
Test Bench
Unit Under Test
Stimulus Signals
Tested Signals
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12. VHDL – Simulation / Verification
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13. VHDL -> Synthesis and P&R
with tmp select j <= w when “1000”, x when “0100”, y when “0010”, z when “0001”, '0‘when others;
VHDL Code
Design Constraints
FPGA list of Components and Connections
NET CLOCK PERIOD = 50 ns;
NET LOAD LOC = P
Synthesis – P&R Tool
FPGA Library of Components
Cyclone
Spartan
Design Attributes
attribute syn_encoding of my_fsm: type is “one-hot”;
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14. Generic VHDL-FPGA Design Flow
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ICTP

15. Design Implemented in the FPGA
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16. FPGA Kit – DE1-SoC
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17. FPGA Kit – DE2-115
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18. FPGA Kit – DE0-Nano-SoC Kit
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19. FPGA Kit – DE0-Nano Kit
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20. FPGA – Xilinx V5
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