1. Remote System Update Example Design for Cyclone IV GX Transceiver Starter Board
April 23rd, 2015 (Rev 1.0)

2. About This Design
This is a design example to demonstrate Cyclone IV remote system upgrade (RSU) feature
It is designed for fallback to realize request from several customer’s
One of two FPGA application images is loaded depending on “page flag bit” in EPCS
Another application image is loaded when configuration fails with the first image
Stop in factory image when configuration fails with both images
Setups
Cyclone IV GX transceiver starter board
EP4CGX15F14, EPCS128
AS configuration
Quartus II build 190

3. Reference Documents Cyclone IV Handbook
Altera Remote Update IP Core User Guide
Altera ASMI Parallel IP Core User Guide
Cyclone IV GX Transceiver Starter Kit User Guide
Cyclone IV GX Transceiver Starter Board Reference Manual

4. Important Notice About board settings About Quartus II settings Others
Board switch-7 (S7) must be ON-OFF-ON-OFF
Erase MAX II data
MAX II asserts nCONFIG when nSTATUS becomes low. It disturbs RSU tests
About Quartus II settings
Assignments  Device  Device and Pin options  Configuration
The settings below are must for both factory and application design
Configuration mode: Remote
Active serial clock source: 20MHz Internal Oscillator
FPGA may fail to configure with 40MHz on this board
Others
Programmer erases and writes only FPGA image area in EPCS, when you program a JIC file
You need to erase all sectors of EPCS in advance to program page bit

5. Files in the Example Package
c4gx_epcs_rsu
prj_factory It is Quartus project directory of factory image
prj_app1 It is Quartus project directory of application1 image
prj_app2 It is Quartus project directory of application2 image
src It contains all verilog source files
factory.v top module of factory image
app1.v top module of application1 image
app2.v top module of application2 image
rsu_top.v wrapper file for RSU IP
led.v module of LED counter
rsu.qsys Qsys file for RSU IP
asmi.qsys Qsys file for ASMI IP
issp.qsys Qsys file for in-system source and probe IP
top.sdc SDC file for all projects

6. Files in the Example Package (Cont’d)
c4gx_epcs_rsu
batch It contains various batch and files for them
all.bat It compiles all projects and generates JIC files
jic.bat It generates JIC files
page#.hex HEX file of page flag that directs to load page# image
page#.cof COF file to generate JIC containing page#.hex
erase.bat It erase all sectors of EPCS
erase.cdf CDF file for erase.bat
pgm#.bat It programs page#.jic
page#.cdf CDF file for pgm#.bat
rsu.stp It is signaltap II file for both factory and application images
rsu.spf It is in-system source and probe file

7. EPCS Memory Map EPCS128 has 64 sectors Each sector consists of 2Mbits
In this design, 10 sectors are allocated for each FPGA image, 1 for “page flag”, and 1 for “retry flag”
n/a
Sector: 31
Address: 0x7C_ x7F_FFFF
Retry flag
Sector: 30
Address: 0x78_ x7B_FFFF
Page flag
Application 2 image
Sector:
Address: 0x50_ x77_FFFF
Application 1 image
Sector:
Address: 0x28_ x4F_FFFF
Factory image
Sector:
Address: 0x00_ x27_FFFF

8. Page Flag and Retry Flag
It is one bit flag, LSB of a byte located in sector 30, or address 0x78_0000
It directs the factory image which application image to be loaded
The user set it, when generating JIC file, or from user application
Retry Flag
It is one bit flag, LSB of a byte located in sector 30, or address 0x7C_0000
It is a working flag that the factory image stores the number of retry after power-up or nCONFIG
It prevents the factory image from triggering reconfiguration forever when both application images are broken
The factory image clear the bit to ‘0’ if it is loaded by power-up or nCONFIG, and sets the bit to ‘1’ if it is loaded by configuration failure

9. Fallback Sequence Factory image Page flag=0? Application 2 image
Power up or
nCONFIG
Factory image
Page flag=0?
Application 2 image No
Clear retry flag to ‘0’
Yes
Application 1 image
Configuration failure
Factory image
Set retry flag to ‘1’
Page flag=0?
Application 1 image No
Yes
Application 2 image
Configuration failure
Factory image
Stop sequence because retry flag is ‘1’

10. Block Diagram
All designs, factory, application1, and application2, have same structure
EP4CGX15
rsu_top
In-System Source and Probe IP
reconfig
read status
Altera Remote Update IP
JTAG
RSU FSM
read
write
erase
check POF
Altera ASMI Parallel IP
EPCS
Main FSM
read flag
12.5MHz
Divider
1/4
led
counter
4 LEDs
CLK 50MHz

11. Factory and Application Images
All four user LEDs blink, when the factory image is loaded
Only user LED-0 (right most) blinks, when the application1 is loaded
Only user LED-1 (left most) blinks, when the application2 is loaded

12. In-System Source and Probe
Bits
Description
Factory
Application
RSU read
All RSU registers are read, when it is changed from 0 to 1
Yes 1
Reconfigure
Reconfiguration is triggered, when it is changed from 0 to 1
n/a 2
Disable watch dog timer reset
Automated WD timer reset is disabled so that application falls back to factory, when it is 1 4
EPCS read
EPCS read to the address specified by [31:8] is triggered, when it is changed from 0 to 1 5
EPCS write
EPCS write to the address specified by [31:8] is triggered, when it is changed from 0 to 1 6
EPCS erase
EPCS erase to the sector specified by [31:8] is triggered, when it is changed from 0 to 1
31:8
EPCS address
39:32
EPCS write data
7,3
reserved

13. Signaltap II

14. Test Setup
You may need to change Quartus II install path in batch files accordingly
Double click all.bat and it compiles all three projects and generates two JIC files
Set up Cyclone IV GX board and connect USB cable to you PC
Check “Notice” in page 4
Open rsu.stp and choose hardware (USB-Blaster)
Open rsu.spf and choose hardware (USB-Blaster)
If you want to use page0 as primary image, run two batches as below and follow the procedure in next page
Double click erase.bat to erase all EPCS sectors
Double click pgm0.bat to program page0.jic
If you want to use page1 as primary image, run two batches as below and follow the procedure in next page
Double click pgm1.bat to program page1.jic

15. Test Procedure
Power off and on the board, and the factory image is loaded
All LEDs will blink to indicate the factory image is successfully loaded
Start signaltap II and it is triggered like shown in the next slide
The application1 image is loaded automatically in a few seconds
Only LED-0 will blink to indicate the application1 image is successfully loaded
Change disable WD timer reset bit (source[2]) from ‘0’ to ‘1’ in in-system source and probe
It prevents application1 image from resetting WD timer
The factory image is loaded again
The application2 image is loaded automatically in a few seconds
It prevents application2 image from resetting WD timer
No application image is loaded because it is second time failure

16. Signaltap II Waveform Example