1. Chapter 4 Field-Effect Transistors
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Microelectronic Circuit Design
McGraw-Hill

2. Depletion-Mode MOSFETS
NMOS transistors with
Ion implantation process used to form a built-in n-type channel in device to connect source and drain by a resistive channel
Non-zero drain current for vGS=0, negative vGS required to turn device off.
Microelectronic Circuit Design
McGraw-Hill

3. Transfer Characteristics of MOSFETS
Plots drain current versus gate-source voltage for a fixed drain-source voltage
Microelectronic Circuit Design
McGraw-Hill

4. Enhancement-Mode PMOS Transistors: Structure
P-type source and drain regions in n-type substrate.
vGS<0 required to create p-type inversion layer in channel region
For current flow, vGS< vTP
To maintain reverse bias on source-substrate and drain-substrate junctions, vSB <0 and vDB <0
Positive bulk-source potential causes VTP to become more negative
Microelectronic Circuit Design
McGraw-Hill

5. Enhancement-Mode PMOS Transistors: Output Characteristics
For , transistor is off.
For more negative vGS, drain current increases in magnitude.
PMOS is in triode region for small values of VDS and in saturation for larger values.
Microelectronic Circuit Design
McGraw-Hill

6. MOSFET Circuit Symbols
(g) and(i) are the most commonly used symbols in VLSI logic design.
MOS devices are symmetric.
In NMOS, n+ region at higher voltage is the drain.
In PMOS p+ region at lower voltage is the drain
Microelectronic Circuit Design
McGraw-Hill

7. Process-defining Factors
Minimum Feature Size, F : Width of smallest line or space that can be reliably transferred to wafer surface using given generation of lithographic manufacturing tools
Alignment Tolerance, T: Maximum misalignment that can occur between two mask levels during fabrication
Microelectronic Circuit Design
McGraw-Hill

8. Mask Sequence for a Polysilicon-Gate Transistor
Mask 1: Defines active area or thin oxide region of transistor
Mask 2: Defines polysilicon gate of transistor, aligns to mask 1
Mask 3: Delineates the contact window, aligns to mask 2.
Mask 4: Delineates the metal pattern, aligns to mask 3.
Channel region of transistor formed by intersection of first two mask layers. Source and Drain regions formed wherever mask 1 is not covered by mask 2
Microelectronic Circuit Design
McGraw-Hill

9. Basic Ground Rules for Layout
F=2 L
T=F/2=L, L could be 1, 0.5, 0.25 mm, etc.
Microelectronic Circuit Design
McGraw-Hill

10. Internal Capacitances in Electronic Devices
Limit high-frequency performance of the electronic device they are associated with.
Limit switching speed of circuits in logic applications
Limit frequency at which useful amplification can be obtained in amplifiers.
MOSFET capacitances depend on operation region and are non-linear functions of voltages at device terminals.
Microelectronic Circuit Design
McGraw-Hill

11. NMOS Transistor Capacitances: Triode Region
Cox” =Gate-channel capacitance per unit area(F/m2).
CGC =Total gate channel capacitance.
CGS = Gate-source capacitance.
CGD =Gate-drain capacitance.
CGSO and CGDO = overlap capacitances (F/m).
Microelectronic Circuit Design
McGraw-Hill

12. NMOS Transistor Capacitances: Triode Region (contd.)
CSB = Source-bulk capacitance.
CDB = Drain-bulk capacitance.
AS and AD = Junction bottom area capacitance of the source and drain regions.
PS and PD = Perimeter of the source and drain junction regions.
Microelectronic Circuit Design
McGraw-Hill

13. NMOS Transistor Capacitances: Saturation Region
Drain no longer connected to channel
Microelectronic Circuit Design
McGraw-Hill

14. NMOS Transistor Capacitances: Cutoff Region
Conducting channel region completely gone.
CGB = Gate-bulk capacitance
CGBO = gate-bulk capacitance per unit width.
Microelectronic Circuit Design
McGraw-Hill

15. SPICE Model for NMOS Transistor
Typical default values used by SPICE:
Kn or Kp = 20 mA/V2
g = 0
l = 0
VTO = 1 V
mn or mp = 600 cm2/V.s
2FF = 0.6 V
CGDO=CGSO=CGBO=CJSW= 0
Tox= 100 nm
Jaeger/Blalock
4/25/07
Microelectronic Circuit Design
McGraw-Hill

16. Microelectronic Circuit Design
Exam 1
HW 1-3 solutions will be posted on website.
Exam 1 is on Tuesday September 17 (6:30-7:30 pm) at EE 129. The exam 1 covers Semiconductor Materials, Diodes, Bipolar Junction Transistors. Field-effect Transistors will not be tested. The exam 1 has 20 questions with multiple choices and heavy calculation like HW1-3. It is 60 minutes (close-book). You are not allowed to look at textbooks, class-notes, etc. by the exam. You are allowed and must use calculator. All "complicated" equations will be given. The exam questions are same as another session since we have the same syllabus. .
I have a special helping time for you to prepare the test. I will have open office hours on Monday (9/21) 2:00pm-5:00pm and Tuesday (9/22) 2:00pm-5:00pm to help you prepare for the exam. Please also use the TAs and Help room as much as possible to prepare your exam.
Jaeger/Blalock
4/25/07
Microelectronic Circuit Design
McGraw-Hill