1. Fig. 1 FETs constructed from densely packed semiconducting CNT arrays.
FETs constructed from densely packed semiconducting CNT arrays. (A) Schematic of CNT array sitting on a SiO2/Si back gate (G) with top Pd source (S) and drain (D) electrodes. (B) False-colored SEM image of a representative FET highlighting where the contacts overlap the CNT array (light orange) and the CNT array channel (dark orange), with Wch = 4.1 μm and Lch = 150 nm. Inset SEM image (scale bar, 200 nm) shows the CNT array, with 47 CNTs μm−1 and a high degree of alignment. (C) TEM cross-sectional image of Pd/CNT/SiO2 electrode stack where the “humps” in the Pd correspond to CNTs in the array. High-resolution TEM images reveal individual CNTs underneath the Pd “humps” with a diameter of 1.3 to 1.9 nm. (D) Atomic force miscroscopy image of 30 nm of Pd overcoating a CNT array, evidencing the conformity of the Pd to the individual CNTs.
Gerald J. Brady et al. Sci Adv 2016;2:e
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