1. IBIS Interconnect Task Group August 23, 2017
Interconnect Modeling – Reference Confusion Bob Ross, Teraspeed Labs
IBIS Interconnect Task Group
August 23, 2017
Copyright 2017 Teraspeed Labs

2. Focus – Legal Splitting of Info in [Interconnect Model Set]
Buffer-to-Pad with Pad-to-Pin [Interconnect Model] connections
I/O and PDN connections (Example 6)
References – especially for I/O connections
Touchstone connections, N+1 terminal reference
How do references connect?
What about mismatched terminal types? Keywords can be used
What about PDN self-referencing? No problem for known N+1 terminal, but not clear with IBIS-ISS
Copyright 2017 Teraspeed Labs

3. [Interconnect Model] Blocks in [Interconnect Model Set]
Buffer-to-Pad
Pad-to-Pin
I/O Paths
PDN Paths (POWER, GND)
Copyright 2017 Teraspeed Labs

4. [Interconnect Model Set] – 16 Reference Combinations
Buffer-to-Pad
Pad-to-Pin
I/O Paths
PDN Paths (POWER, GND)
Copyright 2017 Teraspeed Labs

5. [Interconnect Model Set] – 16 Reference Combinations
Buffer-to-Pad
Pad-to-Pin
I/O Paths
PDN Paths (POWER, GND)
Copyright 2017 Teraspeed Labs

6. [Interconnect Model Set] – 16 Reference Combinations
Buffer-to-Pad
Pad-to-Pin
I/O Paths
PDN Paths (POWER, GND)
Copyright 2017 Teraspeed Labs

7. [Interconnect Model Set] – 16 Reference Combinations
Buffer-to-Pad
Pad-to-Pin
I/O Paths
PDN Paths (POWER, GND)
Copyright 2017 Teraspeed Labs

8. [Interconnect Model Set] – 16 Reference Combinations
Buffer-to-Pad
Pad-to-Pin
I/O Paths
PDN Paths (POWER, GND)
Four Times Four Pad-to-Pin Combinations
Copyright 2017 Teraspeed Labs

9. Example 6, Draft5 11, 12 are illegal, change back to one reference
11 Buffer_Rail signal_name VSS | Reference
Copyright 2017 Teraspeed Labs

10. Page 22, Draft5
Add bus_label and pad_name – they can be reference qualifiers for *_Rails per Table 41 at the selected locations (e.g., bus_label can be used for Buffer_Rail, Pad_Rail, Pin_Rail)
Copyright 2017 Teraspeed Labs

11. Terminal_type_qualifier
Table 41, Draft5
Table 41 – Allowed Terminal_type Associations1
Terminal_type
Terminal_type_qualifier
Aggressor_Only
pin_name
signal_name
bus_label
pad_name
Pin_I/O X A
Pad_I/O
Buffer_I/O
Pin_Rail Y
Pad_Rail Z
Buffer_Rail
Pullup_ref
Pulldown_ref
Power_clamp_ref
Gnd_clamp_ref
Ext_ref
Copyright 2017 Teraspeed Labs

12. One Reference per [Interconnect Model]
Derivation with one reference (all rails shorted to it)
(s2p single reference at VSS creates ideal short for VSS path or forces both the S11 and S22 references to one Terminal_type location – physically different than connections to VSS path endpoints)
Best to include the PDN’s with I/Os for common reference
Copyright 2017 Teraspeed Labs

13. Observations, Questions
How do references connect?
References are not known for IBIS-ISS – can be any rail terminal
N+1 terminal is Touchstone reference
Actual PDN and I/O connections based on known keywords – [Pin Mapping], [Pin], [Die Supply Pads], [Bus Label] for more detail
Do Buffer-to-Pad references connect to Pad-to-Pin references? (Could connect VSS to VDD)
References are confusing to me
Copyright 2017 Teraspeed Labs