1. INF3430 - H131 DCM Location and clock distribution

2. INF3430 - H132 DCM and clock distribution 1

3. INF3430 - H133 Xilinx Digital Clock Manager

4. INF3430 - H134 Xilinx Core Generator

5. INF3430 - H135 Xilinx Core Generator Project

6. INF3430 - H136 Xilinx Gore Generator Project Setup 1

7. INF3430 - H137 Xilinx Core Generator Project Setup 2

8. INF3430 - H138 Generating Single DCM module

9. INF3430 - H139 DCM Setup 1

10. INF3430 - H1310 DCM Setup 2

11. INF3430 - H1311 DCM Setup 3

12. INF3430 - H1312 DCM Setup 4

13. INF3430 - H1313 DCM Setup 5

14. INF3430 - H1314 DCM module Entity library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity clkmng is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end clkmng;

15. INF3430 - H1315 DCM module Architecture architecture BEHAVIORAL of clkmng is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLK0_BUF : std_logic; …… begin CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_INST : DCM generic map( CLK_FEEDBACK => "1X", …… ) port map(CLKFB => CLKFB_IN, CLKIN => CLKIN_IN, …… RST => RST_IN, …… CLKFX => CLKFX_BUF, …… CLK0 => CLK0_BUF, …… LOCKED => LOCKED_OUT, …… ); end BEHAVIORAL;

16. INF3430 - H1316 CRU med clkmng module Entity entity cru is port ( arst : in std_logic; -- Asynch. reset refclk : in std_logic; -- Reference clock; 50 MHz rst : out std_logic; -- Synchronized arst_n for mclk rst_div : out std_logic; -- Synchronized arst_n for mclk_div128 mclk : out std_logic; -- Master clock; 50 MHz pclk : out std_logic; -- Processor clock; 100 MHz mclk_div : out std_logic -- Master clock div. by 128. ); end cru

17. INF3430 - H1317 CRU with clkmng module Architecture : clkmng_0: clkmng port map ( CLKIN_IN => refclk, RST_IN => arst, CLKFX_OUT => pclk, CLK0_OUT => mclk_i, LOCKED_OUT => open); -- Removed in architecture str2 with DCM -- -- bufg_0: bufg -- port map ( -- i => refclk, -- o => mclk_i); :

18. INF3430 - H1318 DCM med ekstra reset logic del 1

19. INF3430 - H1319 DCM med ekstra reset logic del 2